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CXD2720Q-2 Datasheet(PDF) 8 Page - Sony Corporation |
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CXD2720Q-2 Datasheet(HTML) 8 Page - Sony Corporation |
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8 / 47 page  – 8 – CXD2720Q-2 Item RVDT setup time relative to SCK rise RVDT data hold time from SCK rise SCK Low level width SCK High level width XLAT Low level width XLAT High level width SCK rise preceding time relative to XLAT rise SCK rise wait time relative to XLAT rise Delay time to REDY fall relative to XLAT rise. Delay time to REDY fall relative to SCK rise REDY fall preceding time relative to SCK rise REDY rise preceding time relative to XLAT rise REDY rise preceding time relative to SCK fall XLAT fall wait time relative to SCK rise XLAT fall delay time relative to REDY fall Delay time from XLAT rise until TRDT data becomes active Delay time from SCK rise until TRDT data becomes high-impedance Delay time from SCK fall until TRDT data is verified SCK rise wait time for next transmission 20 1 t + 20 1 t + 20 1 t + 20 1 t + 20 1 t + 20 20 3 t + 20 20 20 20 3 t + 20 20 2 t + 40 3 t + 50 4 t + 50 3 t + 80 3 t + 80 2 t + 70 tDS tDH tSWL tSWH tLWL tLWH tSLP tLSD tLBD tSBD tBSP tRLP tRSDP tSLD tLDR tLDN tSDF tSDD tSS Symbol Min. Max. Note 1) t is the cycle of 1/2 the clock frequency applied to the XTLI pin. (384fs) Note 2) REDY and TRDT pins are the values for CL = 60pF. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns |
Similar Part No. - CXD2720Q-2 |
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Similar Description - CXD2720Q-2 |
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