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CXD2720Q-2 Datasheet(PDF) 22 Page - Sony Corporation |
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CXD2720Q-2 Datasheet(HTML) 22 Page - Sony Corporation |
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22 / 47 page  – 22 – CXD2720Q-2 Data section write begins after XLAT rise, and here also transmission must be with LSB first, with tDS and tDH restrictions. In addition, after raising XLAT at the starting point for sending to the data section, wait for 3 t + 20ns or more for the first SCK rise. ( tLSD) When 16 bits (coefficient RAM) or 24 bits (setup register) of this write is repeated, REDY = Low within 4 t + 50ns, and the microcomputer is informed of waiting status for the SV cycle, which is the dedicated data rewrite cycle by microcomputer interface. ( tSBD) When REDY goes High again, the corresponding data is written. The next communication restarts by using the REDY signal as follows. • When REDY = Low, the SCK for the next transmission can rise ( tBSP ≥ 20ns ). • In the same way, when REDY = Low, the XLAT for the next transmission can fall ( tLDR ≥ 20ns). REDY will fall due to this transmission, but it is prohibited for XLAT to rise for the next transmission before the REDY rises. Be sure to raise the next XLAT after REDY rises ( tRLP ≥ 20ns ). In order to restart the next transmission without using the REDY signal, the following conditions must be observed: • There should be 2 t + 40ns or more left between the SCK rise for the final data section and the SCK rise for the next transmission ( tSS). • In the same way, the XLAT for the next transmission can fall after waiting 3 t + 20ns or more after the final data section SCK rise ( tSLD). The tss and tSLD here are shorter times than tSBD ≤ 4t + 50ns, so the restriction conditions are not much strict. However, even in this case the rise of XLAT for the next transmission must come after REDY rise ( tRLP ≥ 20ns). Further, the restriction for XLAT fall at the starting point of this write from tSLD can be: • tSLD ≥ 3t + 20ns if the preceding transmission was “write”. |
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