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CXD2720Q-2 Datasheet(PDF) 21 Page - Sony Corporation |
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CXD2720Q-2 Datasheet(HTML) 21 Page - Sony Corporation |
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21 / 47 page  – 21 – CXD2720Q-2 (4) Details of Communication Methods The definitions of signal timing required for control from the microcomputer are given below. (4)-1. Write First, address section data and mode section data are sent from the microcomputer, synchronized to SCK, to the RVDT pin. The address section data is 8 bits both for the coefficient RAM and setup register, and the setup register transmits optional data for 1 word length. Address section data is sent with LSB first. Mode section data is fixed at 8 bits regardless of content. The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following restrictions: • RV data must be verified before SCK rise ( tDS ≥ 20ns). • RV data must be held for 1 t + 20ns or more after SCK rise (tDH). SCK itself has the following restrictions: • SCK Low level must be 1 t+ 20ns or more (tSWL). • SCK High level must also be 1 t + 20ns or more (tSWH). After raising SCK which corresponds to mode section final data, XLAT is raised ( tSLP ≥ 20ns). XLAT Low level width must be maintained at 1 t + 20ns or more (tLWL). Further, fall timing restrictions are: • for the preceding transmission, if REDY falls due to SCK, as for write, 3 t + 20ns or more is required. (tSLD) • for the preceding transmission, if REDY falls due to XLAT, as for read, 20ns or more is required. ( tLDR) Further, if preceding transmissions have been performed and REDY = Low, it is necessary to wait for REDY = High to raise XLAT. The procedure until this point is the same for write and read. A0 RVDT A7 M0 M7 SQ00 SQ23 A0 M7 SCK XLAT REDY TRDT tDS tDH tSWL tSWH tLSD tSLP tSS tBSP tSLP tSLD tSBD tLDR tRLP tRLP tLWL tLDR tSLD or tLWH High-Z D0/SQ00 D15/SQ23 Figure 6-2. Write Timing |
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