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CXD2586R Datasheet(PDF) 6 Page - Sony Corporation

Part # CXD2586R
Description  CD Digital Signal Processor with Built-in Digital Servo and DAC
Download  127 Pages
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD2586R Datasheet(HTML) 6 Page - Sony Corporation

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CXD2586R/-1
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2/3 frequency division output for MCLK pin. Does not change with variable pitch.
1/4 frequency division output for MCLK pin. Changes with variable pitch.
16.9344MHz output. Changes simultaneously with variable pitch.
Digital Out on/off control. (low: off, high: on)
Digital Out output pin.
Digital GND.
Mute (low: off, high: on)
WFCK (Write Flame Clock) output.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
Sub Q 80-bit and PCM peak and level data 16-bit output.
SQSO readout clock input.
SENS output to CPU.
System reset. Reset when low.
Used during 1-track jumps.
SENS serial data readout clock input.
DFCT switching pin. High: DFCT countermeasure circuit off.
Anti-shock pin.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Track count signal output.
Digital power supply.
Mirror signal output.
Defect signal output.
Focus OK signal output.
Test pin. Not connected.
Spindle motor external pin input.
Spindle motor output filter switching output.
Spindle motor on/off control output.
Spindle motor servo control output.
Spindle motor servo control output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
Disc innermost track detection signal input.
Sled drive output.
Sled drive output.
FSTO
C4M
C16M
MD2
DOUT
DVSS2
MUTE
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
SENS
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
DVDD2
MIRR
DFCT
FOK
TESTA
PWMI
FSW
MON
MDP
MDS
LOCK
SSTP
SFDR
SRON
Pin
No.
Symbol
I/O
Description


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