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CXD2586R Datasheet(PDF) 5 Page - Sony Corporation

Part # CXD2586R
Description  CD Digital Signal Processor with Built-in Digital Servo and DAC
Download  127 Pages
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD2586R Datasheet(HTML) 5 Page - Sony Corporation

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CXD2586R/-1
Pin
No.
37
38
39
40
41
42
43
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
62
63
64
65
66
67
68
69
70
71
72
73
74
75
O
O
O
O
O
O
O
I
O
O
I
O
I
O
I
I
I
I
I
I
I
O
I
I
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Analog
Analog
1, 0
Analog
Analog
1, 0
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
DA03 output when PSSL = 1, MNT2 output when PSSL = 0.
DA02 output when PSSL = 1, MNT1 output when PSSL = 0.
DA01 output when PSSL = 1, MNT0 output when PSSL = 0.
Digital GND.
Analog GND.
Analog power supply.
Channel 2 analog output.
Channel 2 analog input.
Channel 2 LINE output.
Analog GND.
Master clock power supply.
Master clock 33.8688MHz crystal oscillation circuit output.
Master clock 33.8688MHz crystal oscillation circuit output.
Master clock GND.
Analog GND.
Channel 1 LINE output pin.
Channel 1 analog input pin.
Channel 1 analog output pin.
Analog power supply.
Analog GND.
DAC test pin. Normally fixed to high.
DAC test pin. Normally fixed to high.
DAC test pin. Leave this open.
DAC test pin. Leave this open
DAC test pin. Leave this open.
DAC test pin. Leave this open.
DAC test pin. Normally fixed to low.
DAC sync window open input. Normally high, window open when low.
DAC test pin. Normally fixed to low.
DAC test pin. Normally fixed to low.
Crystal selection input.
DSP clock output.
DSP clock input.
2/3 frequency division input for MCLK pin.
DA06
DA05
DA04
DA03
DA02
DA01
DVSS1
AVSS41
AVDD4
AOUT2
AIN2
LOUT2
AVSS42
AVDD5
XTLO
XTLI
AVSS5
AVSS31
LOUT1
AIN1
AOUT1
AVDD3
AVSS32
DTS1
DTS2
DTS3
DTS4
DTS5
DTS6
DTS7
XWO
DAS0
DAS1
XTSL
MCKO
MCLK
FSTI
Symbol
I/O
Description


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