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Z51F0410HCX Datasheet(PDF) 5 Page - Zilog, Inc. |
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Z51F0410HCX Datasheet(HTML) 5 Page - Zilog, Inc. |
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5 / 184 page  Z51F0410 Product Specification PS029502-0212 P R E L I M I N A R Y 2 2.1.3 EEPROM Data Memory .................................................................................................... 44 2.2 SFR Map.................................................................................................................................. 45 2.2.1 SFR Map Summary .......................................................................................................... 45 2.2.2 SFR Map........................................................................................................................... 46 2.2.3 Compiler Compatible SFR ................................................................................................ 49 2.3 I/O Port..................................................................................................................................... 51 2.3.1 I/O Ports............................................................................................................................ 51 2.3.2 Port Register ..................................................................................................................... 51 2.3.3 P0 Port.............................................................................................................................. 52 3. Interrupt Controller ......................................................................................................................... 56 3.1 Overview .................................................................................................................................. 56 3.2 External Interrupt...................................................................................................................... 56 3.3 Block Diagram.......................................................................................................................... 58 3.4 Interrupt Vector Table............................................................................................................... 59 3.5 Interrupt Sequence................................................................................................................... 59 3.6 Effective Timing after Controlling Interrupt bit........................................................................... 61 3.7 Multi Interrupt ........................................................................................................................... 61 3.8 Interrupt Enable Accept Timing ................................................................................................ 63 3.9 Interrupt Service Routine Address............................................................................................ 63 3.10 Saving/Restore General-Purpose Registers........................................................................... 63 3.11 Interrupt Timing ...................................................................................................................... 64 3.12 Interrupt Register Overview.................................................................................................... 64 3.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3).................................................................... 64 3.12.2 Interrupt Priority Register (IP, IP1) .................................................................................. 64 3.12.3 External Interrupt Flag Register (EIFLAG) ...................................................................... 65 3.12.4 External Interrupt Edge Register (EIEDGE) .................................................................... 65 3.12.5 External Interrupt Polarity Register (EIPOLA) ................................................................. 65 3.12.6 External Interrupt Enable Register (EIENAB) .................................................................. 65 3.12.7 Register Map................................................................................................................... 65 3.13 Interrupt Register Description................................................................................................. 65 3.13.1 Register description for Interrupt ..................................................................................... 65 4. Peripheral Hardware....................................................................................................................... 69 4.1 Clock Generator ....................................................................................................................... 69 4.1.1 Overview........................................................................................................................... 69 4.1.2 Block Diagram................................................................................................................... 69 4.1.3 Register Map..................................................................................................................... 70 4.1.4 Clock Generator Register description ............................................................................... 70 4.1.5 Register description for Clock Generator .......................................................................... 70 4.2 BIT ........................................................................................................................................... 72 4.2.1 Overview........................................................................................................................... 72 4.2.2 Block Diagram................................................................................................................... 72 4.2.3 Register Map..................................................................................................................... 72 4.2.4 Bit Interval Timer Register description .............................................................................. 73 4.2.5 Register description for Bit Interval Timer ......................................................................... 73 4.3 WDT......................................................................................................................................... 74 4.3.1 Overview........................................................................................................................... 74 4.3.2 Block Diagram................................................................................................................... 74 4.3.3 Register Map..................................................................................................................... 74 |
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