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Z51F0410HCX Datasheet(PDF) 9 Page - Zilog, Inc. |
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Z51F0410HCX Datasheet(HTML) 9 Page - Zilog, Inc. |
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9 / 184 page  Z51F0410 Product Specification PS029502-0212 P R E L I M I N A R Y 6 List of Figures Figure 1.1 OCD Debugger and Pin Configuration............................................................................... 14 Figure 1.2 Top Abstract Block Diagram .............................................................................................. 15 Figure 1.3 10-SSOP PIN Assignment Diagram of Z51F0410HCX...................................................... 16 Figure 1.7 10-SSOP Package Diagram .............................................................................................. 17 Figure 1.8 USART Pin Location : USART_PINMODE=0 .................................................................... 18 Figure 1.9 USART Pin Location : USART_PINMODE=1 .................................................................... 18 Figure 1.10 I2C Pin Location : I2C_PINMODE=0 ............................................................................... 19 Figure 1.11 I2C Pin Location : I2C_PINMODE=1 ............................................................................... 19 Figure 1.12 External INT Pin Location : EINT_PINMODE=0 .............................................................. 20 Figure 1.13 External INT Pin Location : EINT_PINMODE=1 .............................................................. 20 Figure 1.14 Buzzer Out Pin Location : BUZO_PINMODE=0 .............................................................. 20 Figure 1.15 Buzzer Out Pin Location : BUZO_PINMODE=1 .............................................................. 21 Figure 1.16 Timer Out Pin Location : TMR_PINMODE=0................................................................... 21 Figure 1.17 Timer Out Pin Location : TMR_PINMODE=1................................................................... 21 Figure 1.18 Super Lock Enabled Encryption/Decryption Diagram ...................................................... 22 Figure 1.19 General Purpose I/O Port ................................................................................................ 23 Figure 1.20 External Interrupt I/O Port................................................................................................ 24 Figure 1.21 XIN(SUBXIN) / AN0 /RXD /P0[0] Port Structure .............................................................. 25 Figure 1.22 XOUT(SUBXOUT) / AN1 / INT1 / TXD / P0[1] Port Structure .......................................... 26 Figure 1.23 RESETB / AN2 / ACK / P0[2] Port Structure.................................................................... 27 Figure 1.24 P0[3] / INT0 / SS / EC0 / AN3 / ACOUT Port Structure ................................................... 29 Figure 1.25 P0[4]/SCL/T0O/AN4/AC-/Avref Port Diagram .................................................................. 31 Figure 1.26 P0[5]/SDA/PWM1O/BUZ/AN5/AC+ Port Structure .......................................................... 33 Figure 1.27 P0[6] / AN6, P0[7] / AN7 Port Structure ........................................................................... 35 Figure 1.28 AC Timing ....................................................................................................................... 40 Figure 2.1 Program memory............................................................................................................... 42 Figure 2.2 Data memory map ............................................................................................................. 43 Figure 2.3 Lower 128 bytes RAM ....................................................................................................... 44 Figure 2.4 Debounce Function ........................................................................................................... 55 Figure 3.1 External Interrupt Description ............................................................................................ 57 Figure 3.2 Block Diagram of Interrupt................................................................................................. 58 Figure 3.3 Interrupt Vector Address Table.......................................................................................... 60 Figure 3.4 Effective Timing of Interrupt Enable Register ................................................................... 61 Figure 3.5 Effective Timing of Interrupt Flag Register......................................................................... 61 Figure 3.6 Execution of Multi Interrupt ................................................................................................ 62 Figure 3.7 Interrupt Response Timing Diagram .................................................................................. 63 Figure 3.8 Correspondence between vector Table address and the entry address of ISP ................. 63 Figure 3.9 Saving/Restore Process Diagram & Sample Source ......................................................... 63 Figure 3.10 Timing chart of Interrupt Acceptance and Interrupt Return Instruction............................. 64 Figure 4.1 Clock Generator Block Diagram ........................................................................................ 69 Figure 4.2 BIT Block Diagram ............................................................................................................ 72 Figure 4.3 WDT Block Diagram .......................................................................................................... 74 Figure 4.4 WDT Interrupt Timing Waveform ....................................................................................... 76 Figure 4.5 Watch Timer Block Diagram .............................................................................................. 77 Figure 4.6 8 Bit Timer/Event Counter0, 1 Block Diagram ................................................................... 81 Figure 4.7 Timer/Event Counter0, 1 Example..................................................................................... 82 |
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