R1

V

OUT1

R2

C1

(Optional)

1

2

3

4

16

15

14

13

PVDD2

BOOT2

SW2

PGND2

PVDD1

BOOT1

SW1

PGND1

TPS54290

5

6

7

12

11

10

BP

GND

FB2

EN1

EN2

FB1

8

9

COMP1

COMP2

C2

(Optional)

Z

UPPER

Z

LOWER

C

COMP

R

COMP

UDG-09129

OUT

L

C

C1

R1

´

=

(

)

(

)

OUT

ESR

R1

R2

C2

C

R1 R2

´

+

=

´

´

(

)

KEA

20

LOWER

UPPER

COMP

M

LOWER

10

Z

Z

R

g

Z

´

+

=

´

COMP

POLE

COMP

1

C

2

f

R

=

´ p ´

´

(

)

POLE

LOAD

OUT

1

f

2

2

R

C

=

´ p ´

´

´

TPS54290, TPS54291, TPS54292

www.ti.com

SLUS973 – OCTOBER 2009

Figure 17. Loop Compensation Network

If operating at wide duty cycles (over 50%), a capacitor may be necessary across the upper resistor of the

voltage setting divider. If duty cycles are less than 50%, this capacitor may be omitted.

(8)

If a high ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to

instability. To compensate, a small capacitor is placed in parallel with the lower voltage setting divider resistor.

The value of the capacitor is determined such that a pole is placed at the same frequency as the ESR zero. If

low ESR capacitors are used, this capacitor may be omitted.

(9)

Next, calculate the value of the error amplifier gain setting resistor and capacitor using Equation 10.

(10)

(11)

where

•

NOTE

Once the filter and compensation component values have been established,

laboratory measurements of the physical design should be performed to confirm

converter stability.

Copyright © 2009, Texas Instruments Incorporated

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