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TPS54292 Datasheet(PDF) 19 Page - Texas Instruments |
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TPS54292 Datasheet(HTML) 19 Page - Texas Instruments |
19 / 35 page ![]() TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 LAYOUT RECOMMENDATIONS • The PowerPad must be connected to the low-current ground with available surface copper to dissipate heat. Extending ground land beyond the device package area between PVDD1 (pin 1) and PVDD2 (pin 16) and between COMP1 (pin 8) and COMP2( pin 9) is recommended.. • Connect PGND1 and PGND2 to the PowerPad through a 10-mil wide trace. • Place the ceramic input capacitors near PVDD1 and PVDD2 and bypass to PGND1 and PGND2 respectively. • Locate the inductor near the SW1 or SW2 pin. • Connect the output capacitor grounds to PGND1 or PGND2 with wide, tight loops. • Use a wide ground connection from input capacitor PGND1 or PGND2 as close to power path as possible. It is recommend they be placed directly underneath. • Locate the bootstrap capacitor near the BOOT pin to minimize gate drive loop. • Locate the feedback and compensation components far from switch node and input capacitor ground connection. • Locate the snubber components from SW1 or SW2 to PGND1 or PGND2 close to the device, minimizing the loop area. • Locate the BP bypass capacitor very close to device and bypass to PowerPad. Locate output ceramic capacitor close to inductor output terminal and between inductor and electrolytic capacitors if used. Figure 19. Top Layer Figure 20. Bottom Layer Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link(s) :TPS54290 TPS54291 TPS54292 |
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