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TPS54292 Datasheet(PDF) 18 Page - Texas Instruments |
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TPS54292 Datasheet(HTML) 18 Page - Texas Instruments |
18 / 35 page 0 0.4 0.6 0.8 1.0 1.8 0.2 0 20 40 60 140 80 100 120 T A – Ambient Temperature – °C 0 150 250 500 LFM 1.2 1.6 1.4 LFM = 0 LFM = 150 LFM = 250 LFM = 500 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com POWER DERATING The TPS5429x delivers full current at wide duty cycles at ambient temperatures up to 85°C if the thermal impedance from the thermal pad is sufficient to maintain the junction temperature below the thermal shut down level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction temperature at or below the thermal shutdown level. Figure 18 illustrates the power derating for elevated ambient temperature under various air flow conditions. Note that these curves assume the PowerPAD is soldered to the recommended thermal pad. See References for further information. Figure 18. Power Derating Curves PowerPAD PACKAGE The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. (See Additional References) 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 |
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