– 25 –

CXA1372BQ/BS

CPU Serial Interface Timing Chart

D0

D1

D2

D3

D4

D5

D6

D7

1/fck

DATA

CLK

XLT

Item

Clock frequency

Clock pulse width

Setup time

Hold time

Delay time

Latch pulse width

Symbol

fck

fwck

Min.

500

500

500

1000

1000

Typ.

Max.

Unit

MHz

ns

ns

ns

ns

ns

1

System Control

Focus control

Tracking

control

Tracking mode

Select

D7 D6 D5 D4

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

FS4

Focus

ON

Anti-shock

PS4

Focus

search + 2

PS3

Focus

search + 1

PS2

Sled kick + 2

PS1

Sled kick + 1

FS3

Gain

Down

Brake

ON

FS2

Search

ON

TG2

FS1

Search

Up

TG1

FZC

A. S

TZC

SSTOP

Address

D3

D2

D1

D0

Data

SENS

output

FWD JUMP

REV JUMP

D3

0

0

1

1

D2

0

1

0

1

OFF

ON

FWD MOVE

REV MOVE

D1

0

0

1

1

D0

0

1

0

1

OFF

ON

Item

TG1 and TG2 can be set independently.

When the anti-shock is at 1 (00011xxx), both TG1 and TG2 are inverted when the internal anti-shock is at High.