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CXA1372BS Datasheet(PDF) 15 Page - Sony Corporation |
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CXA1372BS Datasheet(HTML) 15 Page - Sony Corporation |
15 / 32 page – 15 – CXA1372BQ/BS Focus OK circuit 15k 92k VG 54k 20k VCC 0.625V RFO RFI FOK × 1 FOCUS OK AMP FOCUS OK COMPARATOR RF signal 33 39 40 C5 0.01µ The focus OK circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 39 from Pin 40 (RF signal), and the LPF output (opposite phase) of the focus OK amplifier output is also obtained. The focus OK output reverses when VRFI – VRFO ≈ –0.37V. Note that, C5 determines the time constants of the HPF for the EFM comparator and mirror circuit and the LPF of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented. EFM comparator EFM comparator changes RF signal to a binary value. The asymmetry generated due to variations in disc manufacturing cannot be eliminated by the AC coupling alone. Therefore, the reference voltage of EFM comparator is controlled through 1 and 0 that are in approximately equal numbers in the binary EFM signals. As this comparator is a current SW type, each of the High and Low levels is not equal to the power supply voltage. A feedback has to be applied through the CMOS buffer. R8, R9, C8, and C9 form a LPF to obtain (VCC + DGND)/2V. When fc (cut-off frequency) exceeds 500Hz, the EFM low-frequency components leak badly, and the block error rate worsens. 31 C8 C9 ASY R8 R9 CMOS BUFFER CXD2500 100k 20k VC Vcc 40k 40k AUTO ASYMMETRY BUFFER AUTO ASYMMETRY CONTROL AMP 39 RFI EFM COMPARATOR 32 EFM DGND = 0V × 6 |
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