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TSW-102-07-L-D Datasheet(PDF) 17 Page - Texas Instruments |
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TSW-102-07-L-D Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 60 page  www.ti.com 4.8 Clocks Tab 4.8.1 Configuring the codec clocks and Fsref calculation TLV320AIC3104EVM Software Figure 10. Clocks Tab The TLV320AIC3104 provides a phase-locked loop (PLL) that allows flexibility in the clock generation for the ADC and DAC sample rates. The Clocks tab contains the controls that can be used to configure the TLV320AIC3104 for operation with a wide range of master clocks. See the Audio Clock Generation Processing figure in the TLV320AIC3104 data sheet for further details of selecting the correct clock settings. For use with the PC software and the USB-MODEVM, the clock settings must be set a certain way. If the settings are changed from the default settings which allow operation from the USB-MODEVM clock reference, the EVM settings can be restored automatically by pushing the Load EVMS Clock Settings button at the bottom of this tab. Note that changing any of the clock settings from the values loaded when this button is pushed may result in the EVM not working properly with the PC software or USB interface. If an external audio bus is used (audio not driven over the USB bus), then settings may be changed to any valid combination. See Figure 10. The codec clock source is chosen by the CODEC_CLK Source control. When this control is set to CLKDIV_OUT, the PLL is not used; when set to PLLDIV_OUT, the PLL is used to generate the clocks. Note: Per the TLV320AIC3104 data sheet, the codec should be configured to allow the value of Fsref to fall between the values of 39 kHz to 53 kHz. SLAU218 – August 2007 TLV320AIC3104EVM and TLV320AIC3104EVM-PDK 17 Submit Documentation Feedback |
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