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ISO7221CHD Datasheet(PDF) 6 Page - Texas Instruments |
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ISO7221CHD Datasheet(HTML) 6 Page - Texas Instruments |
6 / 16 page IN OUT VO CL Input Generator 50 W VI NOTE A NOTEB V 1/2 CC t f t r 10% 90% 50% 0V 50% VI tPLH tPHL VOH VOL VO V 1/2 CC V 1 CC t fs FAILSAFEHIGH IN OUT 0V or V 1 CC V 1 CC V I C L NOTE A V O V I V O 50% V 1 CC 0V V OH V OL 2.7V VCM IN OUT GND1 NOTE A S1 V orV OH OL V 1 CC V 2 CC C=0.1 F±1% m C=0.1 F±1% m GND2 Pass-failcriteria: Outputmust remainstable OUT Tektronix HFS9009 PATTERN GENERATOR IN DUT Tektronix 784D V 1 CC 0V V / 2 C C Jitter ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT |
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