CY7C1440AV33

Document Number: 38-05383 Rev. *K

Page 21 of 33

Switching Characteristics

Over the Operating Range

Parameter [20, 21]

Description

-250

-167

Unit

Min

Max

Min

Max

1

–1–

ms

Clock

Clock cycle time

4.0

–

6

–

ns

Clock HIGH

1.5

–

2.4

–

ns

Clock LOW

1.5

–

2.4

–

ns

Output Times

Data output valid after CLK rise

–

2.6

–

3.4

ns

Data output hold after CLK rise

1.0

–

1.5

–

ns

Clock to low Z [23, 24, 25]

1.0–

1.5–

ns

Clock to high Z [23, 24, 25]

–

2.6

–

3.4

ns

OE LOW to output valid

–

2.6

–

3.4

ns

OE LOW to output low Z [23, 24, 25]

0

–0–

ns

OE HIGH to output high Z [23, 24, 25]

–

2.6

–

3.4

ns

Set-up Times

Address set-up before CLK rise

1.2

–

1.5

–

ns

ADSC, ADSP set-up before CLK rise

1.2

–

1.5

–

ns

ADV set-up before CLK rise

1.2

–

1.5

–

ns

1.2

–

1.5

–

ns

Data input set-up before CLK rise

1.2

–

1.5

–

ns

Chip enable set-up before CLK rise

1.2

–

1.5

–

ns

Hold Times

Address hold after CLK rise

0.3

–

0.5

–

ns

ADSP, ADSC hold after CLK rise

0.3

–

0.5

–

ns

ADV hold after CLK rise

0.3

–

0.5

–

ns

0.3

–

0.5

–

ns

Data input hold after CLK rise

0.3

–

0.5

–

ns

Chip enable hold after CLK rise

0.3

–

0.5

–

ns

Notes

21. Test conditions shown in (a) of Figure 3 on page 20 unless otherwise noted.

be initiated.

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

high Z prior to low Z under the same system conditions.

25. This parameter is sampled and not 100% tested.