 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CY7C1440AV33 Datasheet(PDF) 1 Page - Cypress Semiconductor |
|
||||||||||||||||||||||||||||||
CY7C1440AV33 Datasheet(HTML) 1 Page - Cypress Semiconductor |
|
|
1 / 33 page  CY7C1440AV33 36-Mbit (1 M × 36) Pipelined Sync SRAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05383 Rev. *K Revised May 14, 2012 36-Mbit (1 M × 36) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250 and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O power supply ■ Fast clock-to-output times ❐ 2.6 ns (for 250-MHz device) ■ Provide high-performance 3-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Single cycle chip deselect ■ CY7C1440AV33 available in Pb-free 100-pin TQFP package, Pb-free 165-ball FBGA package. ■ IEEE 1149.1 JTAG-compatible boundary scan ■ “ZZ” sleep mode option Functional Description The CY7C1440AV33 SRAM integrates 1 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations (see pin descriptions and truth table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1440AV33 operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Description 250 MHz 167 MHz Unit Maximum access time 2.6 3.4 ns Maximum operating current 475 375 mA Maximum CMOS standby current 120 120 mA |
Similar Part No. - CY7C1440AV33_12 |
|
Similar Description - CY7C1440AV33_12 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
