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CY7C1347G Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C1347G Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 25 page  CY7C1347G Document Number: 38-05516 Rev. *L Page 9 of 25 Truth Table The truth table for part number CY7C1347G follow. Next Cycle [1, 2, 3, 4, 5] Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect cycle, power-down None H X X L X L X X X L–H Tristate Deselect cycle, power-down None L L X L L X X X X L–H Tristate Deselect cycle, power-down None L X H L L X X X X L–H Tristate Deselect cycle, power-down None L L X L H L X X X L–H Tristate Deselect cycle, power-down None L X H L H L X X X L–H Tristate Snooze mode, power-down None X X X H X X X X X X Tristate Read Cycle, Begin Burst External L H L L L X X X L L–H Q Read Cycle, Begin Burst External L H L L L X X X H L–H Tristate Write Cycle, Begin Burst External L H L L H L X L X L–H D Read Cycle, Begin Burst External L H L L H L X H L L–H Q Read Cycle, Begin Burst External L H L L H L X H H L–H Tristate Read Cycle, Continue Burst Next X X X L H H L H H L–H Tristate Read Cycle, Continue Burst Next X X X L H H L H L L–H Q Read Cycle, Continue Burst Next H X X L X H L H L L–H Q Read Cycle, Continue Burst Next H X X L X H L H H L–H Tristate Write cycle, continue burst Next X X X L H H L L X L–H D Write cycle, continue burst Next H X X L X H L L X L–H D Read cycle, suspend burst Current X X X L H H H H L L–H Q Read cycle, suspend burst Current X X X L H H H H H L–H Tristate Read cycle, suspend burst Current H X X L X H H H L L–H Q Read cycle, suspend burst Current H X X L X H H H H L–H Tristate Write cycle, suspend burst Current X X X L H H H L X L–H D Write cycle, suspend burst Current H X X L X H H L X L–H D Notes 1. X = “Do not Care.” H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tristate. OE is a do not care for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). |
Similar Part No. - CY7C1347G_12 |
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Similar Description - CY7C1347G_12 |
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