CY7C1347G

Document Number: 38-05516 Rev. *L

Page 7 of 25

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

The CY7C1347G supports secondary cache in systems using

either a linear or interleaved burst sequence. The linear burst

sequence is suited for processors that use a linear burst

sequence. The burst order is user selectable, and is determined

by sampling the MODE input. Accesses can be initiated with

either the Address Strobe from Processor (ADSP) or the Address

Strobe from Controller (ADSC). Address advancement through

the burst sequence is controlled by the ADV input. A two-bit

on-chip wraparound burst counter captures the first address in a

burst sequence and automatically increments the address for the

rest of the burst access.

Byte write operations are qualified with the Byte Write Enable

Enable (GW) overrides all byte write inputs and writes data to all

four bytes. All writes are simplified with on-chip synchronous self

timed write circuitry.

asynchronous Output Enable (OE) provide for easy bank

HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

stored into the address advancement logic and the Address

Register while being presented to the memory core. The

corresponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data is

allowed to propagate through the Output Register and onto the

data bus within 2.6 ns (250 MHz device) if OE is active LOW. The

only exception occurs when the SRAM is emerging from a

deselected state to a selected state, its outputs are always

tristated during the first cycle of the access. After the first cycle

of the access, the outputs are controlled by the OE signal.

Consecutive single read cycles are supported. After the SRAM

is deselected at clock rise by the chip select and either ADSP or

ADSC signals, its output tristates immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions are

advancement logic while being delivered to the RAM core. The

ignored during this first cycle.

ADSP-triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs and DQPs inputs is written into the

corresponding address location in the RAM core. If GW is HIGH,

signals. The CY7C1347G provides byte write capability that is

described in Partial Truth Table for Read/Write on page 10.

Asserting the Byte Write Enable input (BWE) with the selected

bytes.

Bytes not selected during a byte write operation remain

unaltered. A synchronous self timed write mechanism is

provided to simplify the write operations.

Because the CY7C1347G is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQs and DQPs inputs. Doing so tristates the output

drivers. As a safety precaution, DQs and DQPs are automatically

tristated whenever a write cycle is detected, regardless of the

state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following conditions

are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted

appropriate combination of the write inputs (GW, BWE, and

byte(s). ADSC-triggered write accesses require a single clock

the address register and the address advancement logic while

being delivered to the RAM core. The ADV input is ignored

during this cycle. If a global write is conducted, the data

presented to the DQs and DQPs is written into the corresponding

address location in the RAM core. If a byte write is conducted,

only the selected bytes are written. Bytes not selected during a

byte write operation remain unaltered. A synchronous self timed

write mechanism has been provided to simplify the write

operations.

Because the CY7C1347G is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

NC,

NC/9M,

NC/18M,

NC/36M,

NC/72M,

NC/144M,

NC/288M,

NC/576M,

NC/1G

–

No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,

NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the die.

Name

I/O

Description