PACKAGE

(TOP VIEW)

32

31

30

29

19

13

14

15

16

17

18

20

1

2

3

4

5

6

7

8

9

10

11

12

21

22

23

24

28

27

26

25

FAULTZ

SDZ

SYNC

AM0

AM1

MUTE

LINN

LINP

PLIMIT

RINN

GVDD

RINP

AVCC

OUTPR

PVCC

BSPL

GND

OUTPL

PVCC

OUTNL

BSNL

PVCC

OUTNR

BSNR

MODSEL

BSPR

GND

GND

PVCC

GND

GAIN/SLV

AM2

Thermal

PAD

Top

PACKAGE

(TOP VIEW)

32

31

30

29

19

13

14

15

16

17

18

20

1

2

3

4

5

6

7

8

9

10

11

12

21

22

23

24

28

27

26

25

FAULTZ

SDZ

SYNC

AM0

AM1

MUTE

LINN

LINP

PLIMIT

RINN

GVDD

RINP

AVCC

OUTPR

PVCC

BSPL

GND

OUTPL

PVCC

OUTNL

BSNL

PVCC

OUTNR

BSNR

MODSEL

BSPR

GND

GND

PVCC

GND

GAIN/SLV

AM2

Thermal

PAD

Bottom

TPA3116D2

TPA3118D2

TPA3130D2

SLOS708B – APRIL 2012 – REVISED MAY 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

TERMINAL ASSIGNMENT

TPA3116D2

TPA3130D2 and TPA3118D2

32-PIN HTSSOP PACKAGE (DAD)

32-PIN HTSSOP PACKAGE (DAP)

Terminal Functions

PIN

DESCRIPTION

NO.

NAME

1

MODSEL

I

Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to

AVCC.

2

SDZ

I

Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with

compliance to AVCC.

3

FAULTZ

DO

General fault reporting including Over-temp, DC Detect. Open drain.

FAULTZ = High, normal operation

FAULTZ = Low, fault condition

4

RINP

I

Positive audio input for right channel. Biased at 3 V.

5

RINN

I

Negative audio input for right channel. Biased at 3 V.

6

PLIMIT

I

Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly

to GVDD for no power limit.

7

GVDD

PO

Internally generated gate voltage supply. Not to be used as a supply or connected to any component other

than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.

8

GAIN/SLV

I

Selects Gain and selects between Master and Slave mode depending on pin voltage divider.

9

GND

G

Ground

10

LINP

I

Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.

11

LINN

I

Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.

12

MUTE

I

Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic

levels with compliance to AVCC.

13

AM2

I

AM Avoidance Frequency Selection

14

AM1

I

AM Avoidance Frequency Selection

(1)

TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap.

2

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