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TPA3116D2 Datasheet(PDF) 4 Page - Texas Instruments |
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TPA3116D2 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 34 page  + – + – + – + + SDZ MUTE TTL Buffer Gain Control GAIN OUTPR FB RINP RINN Gain Control OUTPNR FB FAULTZ SYNC GAIN/SLV AM<2:0> PLIMIT AVCC GVDD LDO Regulator LINN LINP GND Input Sense PBTL Select OUTPL_FB Gain Control OUTNL_FB AVDD GVDD PLIMIT Reference Ramp Generator Biases and References Startup Protection Logic SC Detect DC Detect Thermal Detect UVLO/OVLO PVCC GVDD PVCC Gate Drive OUTNL_ FB PVCC GVDD PVCC Gate Drive PWM Logic Modulation and PBTL Select OUTPL_FB GND OUTPL BSPL GND OUTNL BSNL GND BSNR OUTPR GND OUTNR OUTNR_ FB BSPR OUTPR_FB PVCC GVDD PVCC Gate Drive PVCC GVDD PVCC Gate Drive PWM Logic Modulation and PBTL Select PLIMIT PLIMIT + – + – + – + – + – + – – – Thermal Pad TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com SYSTEM BLOCK DIAGRAM 4 Copyright © 2012, Texas Instruments Incorporated |
Similar Part No. - TPA3116D2 |
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Similar Description - TPA3116D2 |
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