INA3221

www.ti.com

SBOS576 – MAY 2012

INA3221

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

INPUT

Shunt

–160

159.96

mV

Voltage input range

Bus

0

26

V

CMR

Common-mode rejection

VIN+ = 0 V to +26 V

110

120

dB

±40

±80

μV

Shunt

0.1

0.5

μV/°C

PSRR

15

μV/V

Offset voltage,

±8

±16

mV

Bus

80

μV/°C

PSRR

vs power supply

0.5

mV/V

10

μA

Input bias current

10 || 670

μA || kΩ

(VIN+ pin) + (VIN– pin), power-down mode

0.1

0.5

μA

DC ACCURACY

ADC native resolution

13

Bits

Shunt voltage

40

μV

1-LSB step size

Bus voltage

8

mV

0.1

0.25

%

Shunt

10

50

ppm/°C

Voltage gain error

0.1

0.25

%

Bus

10

50

ppm/°C

DNL

Differential nonlinearity

±0.1

LSB

CT bit = 000

140

154

µs

CT bit = 001

204

224

µs

CT bit = 010

332

365

µs

CT bit = 011

588

646

µs

ADC conversion time

CT bit = 100

1.1

1.21

ms

CT bit = 101

2.116

2.328

ms

CT bit = 110

4.156

4.572

ms

CT bit = 111

8.244

9.068

ms

SMBus

28

35

ms

DIGITAL INPUT/OUTPUT

Input capacitance

3

pF

Leakage input current

0 V

0.1

1

μA

6

V

Input logic levels

–0.5

V

SDA, critical, warning, PV

0

0.4

V

Output logic levels

TC

0

0.4

V

Hysteresis voltage

500

mV

(1)

RTI = Referred-to-input.

(2)

Input leakage is positive (current flows into the pin) for the conditions shown at the top of this table. Negative leakage currents can occur

under different input conditions.

(3)

SMBus timeouts in the INA3221 reset the interface whenever SCL is low for more than 28 ms.

Copyright © 2012, Texas Instruments Incorporated

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