1

1

1

9

9

9

1

0

0

0

0

A1

A0

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Frame 1 Two-Wire Slave Address Byte

(1)

Frame 2 Data MSByte

Frame 3 Data LSByte

Start By

Master

ACK By

INA3221

ACK By

INA3221

Stop By

Master

ACK By

INA3221

SCL

SDA

1

1

1

9

9

9

1

0

0

0

0

A1

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Frame 1 Two-Wire Slave Address Byte

(1)

Frame 2 Data MSByte

Frame 3 Data LSByte

Start By

Master

ACK By

INA3221

ACK By

Master

Stop By

Master

No ACK By

Master

(2)

SCL

SDA

From

INA3221

From

INA3221

INA3221

SBOS576 – MAY 2012

www.ti.com

WRITING TO AND READING FROM THE INA3221

Accessing a specific INA3221 register is accomplished by writing the appropriate value to the register pointer.

Refer to Table 1 for a complete list of registers and corresponding addresses. The value for the register pointer

(refer to Figure 32) is the first byte transferred after the slave address byte with the R/W bit low. Every write

operation to the INA3221 requires a register pointer value.

Register writes begin with the first byte transmitted by the master. This byte is the slave address, with the R/W

bit low. The INA3221 then acknowledges receipt of a valid address. The next byte transmitted by the master is

the register address that data are written to. This register address value updates the register pointer to the

desired register. The next two bytes are written to the register addressed by the register pointer. The INA3221

acknowledges receipt of each data byte. The master may terminate data transfer by generating a start or stop

condition.

When reading from the INA3221, the last value stored in the register pointer by a write operation determines

which register is read during a read operation. To change the register pointer for a read operation, a new value

must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W

bit low, followed by the register pointer byte. No additional data are required. The master then generates a start

condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is

transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte

is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master

acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not-

Acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the

same register are desired, it is not necessary to continually send the register pointer bytes; the INA3221 retains

the register pointer value until it is changed by the next write operation.

Figure 29 and Figure 30 show the write and read operation timing diagrams, respectively. Note that register

bytes are sent most-significant byte first, followed by the least significant byte.

(1)

The value of the Slave Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 7.

Figure 29. Timing Diagram for Write Word Format

(1)

The value of the Slave Address byte is determined by the A0 and A1 pin settings. Refer to Table 7.

(2)

Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated.

See Figure 23.

(3)

An ACK by the master can also be sent.

Figure 30. Timing Diagram for Read Word Format

30

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