1

9

1

0

0

0

0

A1

A0

Frame 1 SMBus ALERT Response

Address Byte

Frame 2 Slave Address Byte

(1)

Start By

Master

ACK By

INA3221

Stop By

Master

No ACK By

Master

(2)

From

INA3221

1

1

0

0

0

0

R/W

SCL

SDA

1

0

9

0

1

1

9

9

1

0

0

0

0

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

Frame 1 Two-Wire Slave Address Byte

(1)

Frame 2 Register Pointer Byte

Start By

Master

ACK By

INA3221

ACK By

INA3221

Stop By

Master

SCL

SDA

INA3221

www.ti.com

SBOS576 – MAY 2012

Figure 31 shows the timing diagram for the SMBus Alert response operation. Figure 32 illustrates a typical

register pointer configuration.

(1)

The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 7.

Figure 31. Timing Diagram for SMBus ALERT

(1)

The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 7.

Figure 32. Typical Register Pointer Set

Copyright © 2012, Texas Instruments Incorporated

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