INA3221

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SBOS576 – MAY 2012

BUS OVERVIEW

essentially compatible with one another.

only when a difference between the two systems is discussed. Two bidirectional lines, the serial clock (SCL) and

data signal line (SDA), connect the INA3221 to the bus. Both SCL and SDA are open-drain connections.

The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.

The bus must be controlled by the master device that generates the SCL, controls the bus access, and

generates start and stop conditions.

To address a specific device, the master initiates a start condition by pulling SDA from a high to a low logic level

while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit

indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed

responds to the master by generating an Acknowledge bit and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data

transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a

start or stop condition.

Once all data are transferred, the master generates a stop condition, indicated by pulling SDA from low to high

while SCL is high. The INA3221 includes a 28-ms timeout on the interface to prevent locking up the bus.

Serial Bus Address

To communicate with the INA3221, the master must first address slave devices with a slave address byte. This

byte consists of seven address bits and a direction bit to indicate whether the intended action is a read or write

operation.

The INA3221 has two address pins, A0 and A1. Table 7 describes the pin logic levels for each of the 16 possible

addresses. The state of the A0 and A1 pins is sampled on every bus communication and should be set before

any activity on the interface occurs.

Table 7. INA3221 Address Pins and Slave Addresses

A0

SLAVE ADDRESS

GND

1000000

1000001

SDA

1000010

SCL

1000011

Serial Interface

open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and

Schmitt triggers to minimize the effects of input spikes and bus noise. While there is spike suppression integrated

into the digital I/O lines, proper layout should be used to minimize the amount of coupling into the communication

lines. This noise introduction could occur from capacitively coupling signal edges between the two

communication lines themselves or from other switching noise sources present in the system. Routing traces in

parallel with ground between layers on a printed circuit board (PCB) typically reduces the effects of coupling

between the communication lines. Shielding communication lines in general is recommended to reduce the

possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or

stop commands.

The INA3221 supports a transmission protocol for Fast (1 kHz to 400 kHz) and High-speed (1 kHz to 3.4 MHz)

modes. All data bytes are transmitted MSB first.

Copyright © 2012, Texas Instruments Incorporated

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