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INA3221AIRGV Datasheet(PDF) 18 Page - Texas Instruments |
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INA3221AIRGV Datasheet(HTML) 18 Page - Texas Instruments |
18 / 36 page ![]() INA3221 SBOS576 – MAY 2012 www.ti.com Overload conditions are another consideration for the INA3221 inputs. The INA3221 inputs are specified to tolerate 26 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long as the power supply or energy storage capacitors can support it). Keep in mind that removing a short to ground can result in inductive kickbacks that can exceed the 26-V differential and common-mode rating of the INA3221. Inductive kickback voltages are best controlled by zener-type transient-absorbing devices (commonly called transzorbs) combined with sufficient energy storage capacitance. In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short is the most likely cause of this event, particularly in applications without large electrolytics present. This problem occurs because an excessive dV/dt can activate the INA3221 ESD protection in systems where large currents are available. Testing has demonstrated that the addition of 10- Ω resistors in series with each INA3221 input sufficiently protects the inputs against this dV/dt failure up to the 26-V device rating. Selecting these resistors in the range noted has minimal effect on accuracy. DEFAULT INA3221 SETTINGS The default register power-up states are listed in the Register Details section. These registers are volatile, and if programmed to a value other than the default values shown in Table 1, they must be reprogrammed every time the device powers up. Software Reset The INA3321 features a software reset that can reinitialize the device and register settings to the default power- up values without having to cycle power to the device. Bit 15 (RESET) of the Configuration Register can be used to perform this software reset. Setting this bit reinitializes all registers and settings to the default power state with the exception of the Power Valid output state. If a software reset is issued, the INA3221 holds the output of the Power Valid pin until the Power Valid detection sequence completes. The Power Valid Upper and Lower limit registers default to the default state when the software reset has been issued so any reprogrammed limit registers are reset, thus resulting in the original Power Valid thresholds validating the Power Valid conditions. This architecture ensures that circuitry connected to the Power Valid output is not interrupted during a software reset event. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): INA3221 |
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