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CDCM6208V1RGZT Datasheet(PDF) 26 Page - Texas Instruments |
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CDCM6208V1RGZT Datasheet(HTML) 26 Page - Texas Instruments |
26 / 78 page VCXO_P VCXO_N Yx_P Yx_N Yx_P Yx_N Yx_P Yx_N Yx_P/N Yx_P/N Differential Differential, Integer Divide Differential, Integer Divide Differential, Fractional Divide Single Ended, Integer Divide Single Ended, Integer Divide tPD, SE tSK,SE,FRAC tPD,DIFF tSK,DIFF,INT tSK,DIFF,FRAC Yx_P/N tSK,SE,INT Single Ended, Fractional Divide VCXO_P Single Ended tSK,SE-DIFF,INT CDCM6208 SCAS931A – MAY 2012 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 25. Differential and Single Ended Output Skew and Propagation Delay DEVICE BLOCK-LEVEL DESCRIPTION The CDCM6208 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a universal input interface, a phase frequency detector (PFD), charge pump, partially integrated loop filter, and a feedback divider. Completing the CDCM6208 device are the combination of integer and fractional output dividers and universal output buffers. The PLL is powered by on-chip low dropout (LDO), linear voltage regulators and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs provide isolation of the PLL from any noise in the external power supply rail with a PSNR of better than -50 dB at all frequencies. The regulator capacitor pin REG_CAP should be connected to ground by a 10 µF capacitor with low ESR (e.g. below 1 Ω ESR) to ensure stability. 26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCM6208 |
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