CDCM6208V1RGZT datasheet(20/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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20 / 78 page

Frequency (Hz)

2.9 ps

-50

10M

10K

100

1000

100k

1M

9.2 ps

0.92 ps

-60

0.29 ps

-70

-100

-80

-90

0.092 ps

-65

-55

-75

-85

-95

Frequency (MHz)

0

60

100

120

140

180

200

400

160

80

20

40

200

250

300

350

all zero, (0) max

MSB-9, (1/1024) typ

MSB-9, (1/1024) max

MSB-4, (1/32) max

MSB-13, (1/16384) max

MSB-13, (1/16384) typ

LSB, (1/1048576) max

LSB, (1/1048576) typ

MSB, (1/2) max

MSB, (1/2) typ

CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

Figure 7. Fractional Divider Bit Selection Impact on TJ

(Maximum Jitter Across Process, Voltage and Temperature)

Tested using a LeCroy 40 Gbps RealTime scope over a time window of 200 ms. The RJ impact on TJ is

estimated for a BERT 10-12-1. This measurement result is overly pessimistic, as it does not bandwidth limit the

high-frequencies. In a real system, the SERDES TX will BW limit the jitter through its PLL roll-off above the TX

PLL bandwidth of typically bit rate divided by 10.

Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

Many system designs become increasingly more sensitive to Power supply noise rejection, in order to simplify

design and cost. The CDCM6208 has built-in internal voltage regulation, which improves the power supply noise

rejection over designs with no regulators. The following output rejection is achieved:

Figure 8. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format (f OUT = 122 MHz)

20

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CDCM6208V1RGZT Datasheet(PDF) 20 Page - Texas Instruments

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