CDCM6208V1RGZT datasheet(2/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k - 20 MHz) or 20 ps-pp

(unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k - 40 MHz) on outputs using

fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k - 20 MHz) or 40 ps-pp on output

using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208 is

packaged in a small 48-pin 7mm x 7mm QFN package.

Additional list of FEATURES

Supply Voltage: The CDCM6208 supply is internally regulated. Therefore each core and I/O supply can be

mixed and matched in any order according to the application needs. The device jitter performance is independent

of supply voltage.

Frequency Range: The PLL includes dual reference inputs with input multiplexer, charge pump, loop filter, and

VCO that operates from 2.39 GHz to 2.55 GHz (CDCM6208V1) and 2.94 GHz to 3.13 GHz (CDCM6208V2).

Reference inputs: The primary and secondary reference inputs support differential and single ended signals

from 8 kHz to 250 MHz. The secondary reference input also supports crystals from 10 MHz to 50 MHz. A 4-bit

reference divider available on the primary reference input. The input mux between the two references supports

simply switching or can be configured as Smart MUX and supports glitchless input switching.

Divider and Prescaler: In addition to the 4-bit input divider of the primary reference a 14-b input divider at the

output of input MUX and a cascaded 8-b and 10-b continuous feedback dividers are available. Two independent

prescaler dividers offer divide by /4, /5 and /6 options of the VCO frequency of which any combination can then

be chosen for a bank of 4 outputs (2 with fractional dividers and 2 that share an integer divider) through an

output MUX. A total of 2 output MUXes are available.

Phase Frequency Detector and Charge Pump: The PFD input frequency can range from 8 kHz to 100 MHz.

The charge pump gain is programmable and the loop filter consists of internal + partially external passive

components and supports bandwidths from a few Hz up to 400kHz.

Phase Noise: The Phase Noise performance of the device can be summarized to:

Table 1. Synthesizer Mode (Loop filter BW >250 kHz)

Random Jitter (all outputs)

Total Jitter

Typical

Maximum

Integer divider

Fractional divider

DJ-unbound

DJ 10k-40MHz

10k-20MHz

10k-100MHz

RJ 10k-20MHz

0.27 ps-rms (Integer division)

50-220 ps-pp,

0.5 ps-rms (int div)

0.625 ps-rms (int div)

20 ps-pp (1)

0.7ps-rms (fractional div)

see Figure 4

(1)

TJ = 20 pspp applies for LVPECL, CML, and LVDS signaling. TJ lab characterization measured 8 pspp, (typical) and 12 pspp (max) over

PVT.

Table 2. Jitter Cleaner Mode (Loop filter BW < 1 kHz)

Random Jitter (all outputs)

Total Jitter

Typical

Maximum

Integer divider

Fractional divider

DJ unbound

DJ 10k-40MHz

10k-20MHz

10k-100MHz

RJ 10k-20MHz

1.6 ps-rms (Integer division)

70-240 ps-pp,

2.1 ps-rms (int div)

2.14 ps-rms (int div)

40 ps-pp

2.3 ps-rms (fractional div) 10k-20MHz

see Figure 4

2

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