CDCM6208V1RGZT datasheet(16/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

OUTPUT SKEW AND SYNC TO OUTPUT PROPAGATION DELAY CHARACTERISTICS

VDD_Yx_Yy = 1.71 TO 1.89 V, 2.375 V TO 2.625 V, 3.135V TO 3.465 V, TA = -40°C TO 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

PS_A=4

9

10.5

11

1/f PS_A

V1: f VCO= 2.5 GHz

PS_A=5

9

10.2

11

1/f PS_A

PS_A=6

9

10.0

11

1/f PS_A

Propagation delay SYNCN

↑

tPD-PS

to output toggling high

PS_A=4

10

10.9

12

1/f PS_A

V2: f VCO= 3 GHz

PS_A=5

9

10.5

11

1/f PS_A

PS_A=6

9

10.2

11

1/f PS_A

Part-to-Part Propagation

ΔtPD-PS

delay variation SYNCN

↑ to

Fixed supply voltage, temp, and device setting(1)

0

1 1/f PS_A

output toggling high(1)

Output Skew – all outputs use identical output signaling, integer dividers only; PS_A = PS_B = 6, OutDiv = 4

tSK,LVDS

Skew between Y[7:4] LVDS

Y[7:4] = LVDS

40

ps

tSK,LVDS

Skew between Y[3:0] LVDS

Y[3:0] = LVDS

40

ps

tSK,LVDS

Skew between Y[7:0] LVDS

Y[7:0] = LVDS

80

ps

tSK,CML

Skew between Y[3:0] CML

Y[3:0] = CML

40

ps

tSK,PECL

Skew between Y[3:0] PECL

Y[3:0] = LVPECL

40

ps

tSK,HCSL

Skew between Y[7:4] HCSL

Y[7:4] = HCSL

40

ps

tSK,SE

Skew between Y[7:4] CMOS

Y[7:4] = CMOS

50

ps

Output Skew - mixed signal output configuration, integer dividers only; PS_A = PS_B = 6, OutDiv = 4

Skew between Y[7:4] LVDS

tSK,CMOS-LVDS

Y[4] = CMOS, Y[7:5] = LVDS

2.5

ns

and CMOS mixed

Skew between Y[7:0] CMOS

tSK,CMOS-PECL

Y[7:4] = CMOS, Y[3:0] = LVPECL

2.5

ns

and LVPECL mixed

Skew between Y[3:0]

tSK,PECL-LVDS

Y[0] = LVPECL, Y[3:1] = LVDS

120

ps

LVPECL and LVDS mixed

Skew between Y[3:0]

tSK,PECL-CML

Y[0] = LVPECL, Y[3:1] = CML

40

ps

LVPECL and CML mixed

Skew between Y[7:0] LVDS

tSK,LVDS-PECL

Y[7:4] = LVDS, Y[3:0] = LVPECL

180

ps

and LVPECL mixed

Skew between Y[7:4] LVDS

tSK,LVDS-HCSL

Y[4] = LVDS, Y[7:5] = HCSL

250

ps

and HCSL mixed

Output skew - using fractional output division; PS_A = PS_B = 6, OutDiv = 3.125

Skew between Y[7:4] LVDS

tSK,DIFF, frac

using all fractional divider

Y[7:4] = LVDS

200

ps

with the same divider setting

(1)

SYNC is toggled 10,000 times for each device. Test is repeated over PVT.

16

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