CDCM6208V1RGZT datasheet(15/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

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SCAS931A – MAY 2012 – REVISED JUNE 2012

HCSL OUTPUT CHARACTERISTICS

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 TO 1.89 V, 2.375 V TO 2.625 V,3.135 V TO 3.465

V, TA = -40 °C TO 85 °C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V1

1.55

400

fOUT-I

Output Frequency

Integer Output Divider

MHz

V2

1.91

400

fOUT-F

Output Frequency

Fractional Output Divider

0.78

400

MHz

fACC-F

Output Frequency Error (1)

Fractional Output Divider

-1

1

ppm

Output Common Mode

VCM

VDD_Yx_Yy = 2.5/3.3 V

0.2

0.34

0.55

V

Voltage

VDD_Yx_Yy = 1.8 V

0.2

0.33

0.55

V

|VOD|

Differential Output Voltage

VDD_Yx_Yy = 2.5/3.3 V;

0.4

0.67

1.0

V

|VOD|

Differential Output Voltage

VDD_Yx_Yy = 1.8 V

0.4

0.65

1.0

V

Differential Output Peak-to-

VDD_Yx_Yy = 2.5/3.3 V

1.0

2.1

V

peak Voltage

VOUT

Differential Output Peak-to-

2 x|V

VDD_Yx_Yy = 1.8 V

V

peak Voltage

OD|

measured from VDIFF= -100 mV to VDIFF = +100mV,

tR/tF

Output Rise/Fall Time

100

167

250

ps

VDD_Yx_Yy = 2.5/3.3 V

measured from VDIFF= -100 mV to VDIFF= +100 mV,

tR/tF

Output Rise/Fall Time

120

192

295

ps

VDD_Yx_Yy = 1.8 V

-158.8

-153

dBc/Hz

PN-floor

Phase Noise Floor

fOUT = 122.88 MHz

VDD_Yx = 2.5/3.3 V

-157.6

-153

dBc/Hz

ODC

Output Duty Cycle

Not in bypass mode

45%

55%

(1)

The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach

of a ½ 20multiple, the actual output frequency error is 0.

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