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CDCM6208V1RGZT Datasheet(PDF) 14 Page - Texas Instruments

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Part # CDCM6208V1RGZT
Description  2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCM6208V1RGZT Datasheet(HTML) 14 Page - Texas Instruments

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CDCM6208
SCAS931A – MAY 2012 – REVISED JUNE 2012
www.ti.com
CML OUTPUT CHARACTERISTICS
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V TO 1.89 V, 2.375V TO 2.625 V, 3.135 V TO
3.465 V, TA = -40 °C TO 85 °C
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V1
1.55
800
fOUT-I
Output Frequency
Integer Output Divider
MHz
V2
1.91
800
Output AC coupled Common
VDD_Yx_Yy –
VCM-AC
AC coupled with 50
Ω receiver termination
V
Mode Voltage
0.46
Output DC coupled Common
DC coupled with 50
Ω on-chip termination to
VDD_Yx_Yy –
VCM-DC
V
Mode Voltage
VDD_Yx_Yy
0.2
|VOD|
Differential Output Voltage
100
Ω diff load AC coupling, (Figure 12)
0.3
0.45
0.58
V
Differential Output Peak-to-
2 x |V
VOUT
V
peak Voltage
OD|
VDDYx = 1.8 V
100
151
300
ps
tR/tF
Output Rise/Fall Time
20% to 80%
VDDYx = 2.5 V/3.3 V
100
143
200
ps
VDD_Yx_Yy = 1.8 V
-161.2-
-155.8
dBc/Hz
Phase Noise Floor at > 5 Hz
PN-floor
fOUT = 122.88 MHz
offset
VDD_Yx_Yy = 3.3 V
161.2
-153.8
dBc/Hz
ODC
Output Duty Cycle
Not in bypass mode
47.5%
52.5%
ROUT
Output Impedance
measured from pin to VDD_Yx_Yy
50
Ω
LVDS (LOW-POWER CML) OUTPUT CHARACTERISTICS
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V TO 1.89 V, 2.375 V TO 2.625 V,3.135 V TO
3.465 V, TA = -40 °C TO 85 °C
PARAMETER
TEST CONDITIONS
MINI
TYP
MAX
UNITS
CDCM6208V1
1.55
400
fOUT-I
Output Frequency
Integer Output Divider
MHz
CDCM6208V2
1.91
400
fOUT-F
Output Frequency
Fractional Output Divider
0.78
400
MHz
fACC-F
Output Frequency Error (1)
Fractional Output Divider
-1
1
ppm
Output AC coupled Common
VDD_Yx_Yy –
VCM-AC
AC coupled with 50
Ω receiver termination
V
Mode Voltage
0.76
Output DC coupled Common
DC coupled with 50
Ω on-chip termination to
VDD_Yx_Yy –
VCM-DC
V
Mode Voltage
VDD_Yx_Yy
0.13
|VOD|
Differential Output Voltage
100
Ω diff load AC coupling, (Figure 12)
0.247
0.34
0.454
V
Differential Output Peak-to-
2 x |V
VOUT
V
peak Voltage
OD|
tR/tF
Output Rise/Fall Time
± 100mV around crossing point
300
ps
VDD_Yx = 1.8 V
-159.3
-154.5
dBc/Hz
PN-floor
Phase Noise Floor
fOUT= 122.88 MHz
VDD_Yx = 2.5/3.3 V
-159.1
-154.9
dBc/Hz
Y[3:0]
47.5%
52.5%
ODC
Output Duty Cycle
Not in bypass mode
Y[7:4]
45%
55%
ROUT
Output Impedance
Measured from pin to VDD_Yx_Yy
167
Ω
(1)
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a multiple of 1 over 220, the actual output frequency error is 0.
14
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): CDCM6208


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