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CDCM6208V1RGZT Datasheet(PDF) 13 Page - Texas Instruments

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Part # CDCM6208V1RGZT
Description  2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCM6208V1RGZT Datasheet(HTML) 13 Page - Texas Instruments

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CDCM6208
www.ti.com
SCAS931A – MAY 2012 – REVISED JUNE 2012
LVCMOS OUTPUT CHARACTERISTICS (continued)
VDD_Yx_Yy = 1.71 V TO 1.89V, 2.375 V TO 2.625 V, 3.135 V TO 3.465 V, TA = -40 °C TO 85 °C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output Rise/Fall Slew Rate
20% to 80%, VDD_Yx_Yy =
5.37
V/ns
(normal mode)
2.5/3.3 V, CL = 5 pF
tSLEW-RATE-N
Output Rise/Fall Slew Rate
20% to 80%, VDD_Yx_Yy = 1.8 V,
2.62
V/ns
(normal mode)
CL = 5 pF
Output Rise/Fall Slew Rate (slow
20% to 80%, VDD_Yx_Yy =
4.17
V/ns
mode)
2.5/3.3 V, CL = 5 pF
tSLEW-RATE-S
Output Rise/Fall Slew Rate (slow
20% to 80%, VDD_Yx_Yy = 1.8 V,
1.46
V/ns
mode)
CL = 5 pF
PN-floor
Phase Noise Floor
fOUT = 122.88 MHz
-159.5
-154
dBc/Hz
ODC
Output Duty Cycle
Not in bypass mode
45%
55%
V OUT = VDD_Yx/2
ROUT
Output Impedance
Normal mode
30
50
90
Ω
Slow mode
45
74
130
Ω
LVPECL (HIGH-SWING CML) OUTPUT CHARACTERISTICS
VDD_Yx_Yy = 2.375 V TO 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V TO 1.89 V, 2.375 V TO
2.625 V, 3.135 V TO 3.465 V, TA = -40 °C TO 85 °C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CDCM6208V1
1.55
800
fOUT-I
Output Frequency
Integer Output Divider
MHz
CDCM6208V2
1.91
800
Output DC coupled Common
DC coupled with 50
Ω external termination to
VCM-DC
VDD_Yx_Yy – 0.4
V
Mode Voltage
VDD_Yx_Yy
100
Ω diff load AC coupling (Figure 12), fOUT ≤ 250
MHz
VDD_Yx_Yy
≤ 1.89
0.45
0.75
1.12
V
VDD_Yx_Yy
≤ 2.375
0.6
0.8
1.12
V
|VOD|
Differential Output Voltage
100
Ω diff load AC coupling (Figure 12), fOUT ≤ 250
MHz
VDD_Yx_Yy = 1.8 V
0.73
V
VDD_Yx_Yy
≤ 3.135
0.55
0.75
1.12
V
Differential Output Peak-to-
2 x |V
VOUT
V
peak Voltage
OD|
±200 mV around crossing point
109
217
ps
tR/tF
Output Rise/Fall Time
20% to 80% VOD
211
ps
tslew
Output rise/fall slew rate
3.7
5.1
7.3
V/ns
PN-floor
Phase Noise Floor
VDD_Yx_Yy = 3.3 V see Figure 41
-161.4
-155.8
dBc/Hz
ODC
Output Duty Cycle
Not in bypass mode
47.5%
52.5%
ROUT
Output Impedance
measured from pin to VDD_Yx_Yy
50
Ω
Copyright © 2012, Texas Instruments Incorporated
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