CDCM6208V1RGZT datasheet(12/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

PLL CHARACTERISTICS

VDD_PLLx, VDD_VCO = 1.71 V TO 1.89 V, 2.375 V TO 2.625 V, 3.135 V TO 3.465 V, TA = -40 °C TO 85 °C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V1

2.39

2.55

fVCO

VCO Frequency Range

GHz

V2

2.94

3.13

V1, 2.39 GHz

178

V1, 2.50 GHz

204

V1, 2.55 GHz

213

KVCO

VCO Gain

MHz/V

V2, 2.94 GHz

236

V2, 3.00 GHz

250

V2, 3.13 GHz

283

fPFD

PFD Input Frequency

0.008

100

MHz

High Impedance Mode Charge

ICP-L

±700

nA

Pump Leakage

Measured in-band phase noise at

Estimated PLL Figure of Merit

fFOM

the VCO output minus 20log(N-

-224

dBc/Hz

(FOM)

divider) at the flat region

Power supply ramp time of 1ms from

0 V to 1.7 V, final frequency

accuracy of 10 ppm, fPFD = 25 MHz,

CDCM6208V1 pin mode use case

tSTARTUP

Startup time (see Figure 29 )

#2, CPDN_to_GND = 22nF

w/ PRI input signal

12.8

ms

w/ NDK 25 MHz crystal

12.85

ms

LVCMOS OUTPUT CHARACTERISTICS

VDD_Yx_Yy = 1.71 V TO 1.89V, 2.375 V TO 2.625 V, 3.135 V TO 3.465 V, TA = -40 °C TO 85 °C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Fract Out divVDD_Yx_Yy =

0.78

250

2.5/3.3 V

Integer out divVDD_Yx_Yy =

fOUT-F

Output Frequency

1.55

250

MHz

2.5/3.3 V

Int or frac out divVDD_Yx_Yy =

0.78/1.5

200

1.8 V

fACC-F

Output Frequency Error (1)

Fractional Output Divider

-1

1

ppm

0.8 x

Output High Voltage (normal

VDD_Yx = min to max, IOH = -1

VOH

VDD_Yx_

V

mode)

mA

Yy

0.2 x

VDD_Yx = min to max, IOL = 100

VOL

Output Low Voltage(normal mode)

VDD_Yx_

V

µA

Yy

0.7 x

VDD_Yx = min to max, IOH = -100

VOH

Output High Voltage (slow mode)

VDD_Yx_

V

µA

Yy

0.3 x

VDD_Yx = min to max, IOL = 100

VOL

Output Low Voltage(slow mode)

VDD_Yx_

V

µA

Yy

V OUT = VDD_Yx_Yy/2

IOH

Output High Current

Normal mode

-50

-8

mA

Slow mode

-45

-5

mA

V OUT = VDD_Yx_Yy/2

IOL

Output Low Current

Normal mode

10

55

mA

Slow mode

5

40

mA

(1)

The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach

of a multiple 1 over 220, the actual output frequency error is 0.

Note: In LVCMOS Mode, positive and negative outputs are in phase.

12

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