CDCM6208V1RGZT datasheet(69/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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CDCM6208 Reference Schematic

December, 2011

Title

Rev

Date:

Sheet

of

C1

R86

49.9

C296

1uF

R_SEC_PDN

R73

DNI

R_PRI_PUP

C28

4pF

C297

1uF

C2

R83

49.9

R84

49.9

R72

DNI

R89

0.0

R85

49.9

R_SEC_PUP

R_PRI_PDN

C27

4pF

C_PRI_N

1uF

C29

1uF

C_PRI_P

1uF

R87

0.0

C30

1uF

R2

Y1

NX3225GA

1

GND1

2

3

GND0

4

25MHz

VDD_SEC_IN

CLKIN_SECP

CLKIN_SECN

VDD_PRI_IN

CLKIN_PRIP

CLKIN_PRIN

PRI_REFP

PRI_REFN

SEC_REFP

SEC_REFN

ELF

PRIMARY REFERENCE INPUT

SECONDARY REFERENCE INPUT

Loop Filter

Examples:

LOOP FILTER

Synthesizer mode (high loop bandwidth)

CDCM6208V1:

With C1=100pF, R2=500Ö, C2=22nF and

Internal components R3=100Ö, C3=242.5pF,

fPFD=25MHz, and ICP=2.5mA:

Loop bandwidth ~ (300kHz)

CDCM6208V2:

With C1=470pF, R2=560Ö, C2=100nF and

Internal components R3=100Ö, C3=242.5pF,

fPFD=30.72MHz, and ICP=2.5mA:

Loop bandwidth ~ (300kHz)

Jitter cleaner mode (low loop bandwidth):

CDCM6208V1:

With C1=4.7éF, R2=145Ö, C2=47éF and

Internal components R3=4.01kÖ, C3=662.5pF,

fPFD=40kHz, and ICP=500éA:

Loop bandwidth ~ (40Hz)

CDCM6208V2:

With C1=5éF, R2=100Ö, C2=100éF and

Internal components R3=4.01kÖ, C3=662.5pF,

fPFD=80kHz, and ICP=500éA:

Loop bandwidth ~ (100Hz)

2

3

The following input biasing is recommended:

AC coupled differential signals with VDD_PRI/SEC=2.5/3.3V:

select Reg4[7:6]=01 and/or Reg4[4:3]=01 (LVDS),

target VBIAS=1.2V, therefore

set R_PRI_PUP=5.5k, RPRI_PDN=3.14k

DC coupled LVDS signals with VDD_PRI/SEC=2.5/3.3V:

select Reg4[7:6]=01 and/or Reg4[4:3]=01 (LVDS),

R_PRI_PUP=5.5k, RPRI_PDN=3.14k

replace C_PRI_P=C_PRI_N=0Ö

DC coupled 3.3V CMOS signals:

Connect VDD_SEC_IN=3.3V,

select Reg4[7:6]=10 and/or Reg4[4:3]=10 (CMOS),

R83,R84,R85, & R86=DNI, replace C_PRI_P=C_PRI_N=0Ö

for VDD_PRI/SEC=1.8V:

target VBIAS=0.9V, therefore

set R_PRI_PUP=5.5k, RPRI_PDN=5.5k

for VDD_PRI/SEC=1.8V:

R_PRI_PUP=5.5k, RPRI_PDN=3.14k

for 1.8V CMOS signals:

Connect VDD_SEC_IN=1.8V:

DC coupled CML only (VDD_PRI/6(& YROWDJH LV GRQ¬W FDUH):

select Reg4[7:6]=00 and/or Reg4[4:3]=00 (CML),

set R_PRI_PUP=0Ö, RPRI_PDN=DNI,

Replace CPRI_P=0Ö, C_PRI_N=0Ö

Use of Crystal on secondary reference input (VDD_SEC_,1 YROWDJH LV GRQ¬W FDUH):

select Reg4[7:6]=11 (XTAL),

set R87=DNI, R89=DNI, R72=0Ö, R73=0Ö

CDCM6208

www.ti.com

SCAS931A – MAY 2012 – REVISED JUNE 2012

Figure 54. Schematic page 2

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