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CDCM6208V1RGZT Datasheet(PDF) 66 Page - Texas Instruments |
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CDCM6208V1RGZT Datasheet(HTML) 66 Page - Texas Instruments |
66 / 78 page CDCM6208 SCAS931A – MAY 2012 – REVISED JUNE 2012 www.ti.com Table 40. Register 21 (Read Only) (continued) BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 4 RESERVED This bit will read a 0 3 RESERVED This bit will read a 0 Indicates unlock status for PLL (digital): 0 → PLL locked 1 → PLL unlocked 2 PLL_UNLOCK Note: the external output signal on Status 0 or Status 1 uses a reversed logic, and indicates "lock" with a VOH signal and unlock with a VOL signaling level. Device Status Loss of reference input observed at input Smart MUX output in Monitoring observation window for PLL: 1 LOS_REF 0 → Reference input present 1 → Loss of reference input Indicates Reference Selected for PLL: 0 SEL_REF 0 → Primary 1 → Secondary Table 41. Register 40 (Read Only) BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 15 RESERVED Ignore 14 RESERVED Ignore 13 RESERVED Ignore 12 RESERVED Ignore 11 RESERVED Ignore 10 RESERVED Ignore 9 RESERVED Ignore 8 RESERVED Ignore 7 RESERVED Ignore 6 RESERVED Ignore Indicates the device version (Read only): 5:3 VCO_VERSION 000 → CDCM6208V1 001 → CDCM6208V2 Device Information Indicates the silicon die revision (Read only): 2:0 DIE_REVISION 000 → PG1.0 (engineering silicon) 001 → PG2.2 (final silicon) Table 42. Default Register Setting For SPI/I2C Modes Register CDCM6208V1 CDCM6208V2 0 0x01B8 0x01B8 1 0x0000 0x0000 2 0x0018 0x0013 3 0x08F4 0x08F5 4 0x30EC 0x30EC 5 0x0132 0x0022 6 0x0003 0x0003 7 0x0022 0x0022 8 0x0003 0x0004 9 0x0202 0x0002 10 0x003B 0x0090 11 0x01EC 0x0000 12 0x0202 0x0002 13 0x003B 0x0090 66 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCM6208 |
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