CDCM6208V1RGZT datasheet(63/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

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SCAS931A – MAY 2012 – REVISED JUNE 2012

Table 31. Register 12

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15

RESERVED

This bit must be set to 0

Output MUX setting for output channel 5:

00 and 11

→ PLL

14:13

OUTMUX_CH5[1:0]

01

→ Primary input

10

→ Secondary input

Output channel 5 fractional divider's 3-b pre-divider setting(this pre-

divider is bypassed if Q12.9 = 0)

000

→ Divide by 2

12:10

PRE_DIV_CH5[2:0]

001

→ Divide by 3

111

→ Divide by 1; (only for CDCM6208V1 with fVCO ≤ 2.4GHz)

All other combinations reserved

Output channel 5 fractional divider enable:

9

EN_FRACDIV_CH5

0

→ Disable

1

→ Enable

Output channel 5 LVCMOS output slew:

8

LVCMOS_SLEW_CH5

0

→ Normal

1

→ Slow

Output channel 5 negative-side LVCMOS enable:

0

→ Disable

7

EN_LVCMOS_N_CH5

Output Channel 5

1

→ Enable (Negative side can only be enabled if positive side is

enabled)

Output channel 5 positive-side LVCMOS enable:

6

EN_LVCMOS_P_CH5

0

→ Disable

1

→ Enable

5

RESERVED

This bit must be set to 0

Output channel 5 type selection:

00 or 01

→ LVDS

4:3

SEL_DRVR_CH5[2:0]

10

→ LVCMOS

11

→ HCSL

Output channel 5 enable:

00

→ Disable

2:1

EN_CH5[1:0]

01

→ Enable

10

→ Drive static 0

11

→ Drive static 1

Output channel 5Supply Voltage Selection:

0

SUPPLY_CH5 (1)

0

→ 1.8 V

1

→ 2.5/3.3 V

(1)

It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 32. Register 13

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15

RESERVED

This bit must be set to 0

14

RESERVED

This bit must be set to 0

13

RESERVED

This bit must be set to 0

12

RESERVED

This bit must be set to 0

Output channel 5 8-b integer divider setting

11:4

OUTDIV5[7:0]

(Divider value is register value +1)

Output Channel 5

3:0

FRACDIV5[19:16]

Output channel 5 20-b fractional divider setting, bits 19-16

Table 33. Register 14

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15:0

FRACDIV5[15:0]

Output Channel 5

Output channel 5 20-b fractional divider setting, bits 15-0

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