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CDCM6208V1RGZT Datasheet(PDF) 61 Page - Texas Instruments |
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CDCM6208V1RGZT Datasheet(HTML) 61 Page - Texas Instruments |
61 / 78 page CDCM6208 www.ti.com SCAS931A – MAY 2012 – REVISED JUNE 2012 Table 26. Register 7 BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 15 RESERVED This bit must be set to 0 14 RESERVED This bit must be set to 0 13 RESERVED This bit must be set to 0 12 RESERVED This bit must be set to 0 11 RESERVED This bit must be set to 0 10 RESERVED This bit must be set to 0 9 RESERVED This bit must be set to 0 Output Channel 3 Type Selection: 00, 01 → LVDS 8:7 SEL_DRVR_CH3[1:0] 10 → CML 11 → PECL Output Channel 3 Output channel 3 enable: 00 → Disable 6:5 EN_CH3[1:0] 01 → Enable 10 → Drive static 0 11 → Drive static 1 Output Channel 2 Type Selection: 00, 01 → LVDS 4:3 SEL_DRVR_CH2[1:0] 10 → CML" 11 → PECL Output Channel 2 Output channel 2 enable: 00 → Disable 2:1 EN_CH2[1:0] 01 → Enable 10 → Drive static 0 11 → Drive static 1 Output Channels 2 and 3 Supply Voltage Selection: Output Channels 2 0 SUPPLY_CH2_3 (1) 0 → 1.8 V and 3 1 → 2.5/3.3 V (1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter. Table 27. Register 8 BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 15 RESERVED This bit must be set to 0 14 RESERVED This bit must be set to 0 13 RESERVED This bit must be set to 0 12 RESERVED This bit must be set to 0 11 RESERVED This bit must be set to 0 10 RESERVED This bit must be set to 0 9 RESERVED This bit must be set to 0 8 RESERVED This bit must be set to 0 Output Channels 2 Output channels 2 and 3 8-b output integer divider setting 7:0 OUTDIV2_3[7:0] and 3 (Divider value is register value +1) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 61 Product Folder Link(s): CDCM6208 |
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