CDCM6208V1RGZT datasheet(60/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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60 / 78 page

CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

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Table 23. Register 4 (continued)

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

Supply voltage for secondary input:

1

SEC_SUPPLY (1)

Secondary Input

0

→ 1.8 V

1

→ 2.5/3.3 V

Supply voltage for primary input:

0

PRI_SUPPLY (2)

Primary Input

0

→ 1.8 V

1

→ 2.5/3.3 V

(1)

It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers

should be updated after power-up to reflect the true VDD_SEC supply voltage used.

(2)

It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers

should be updated after power-up to reflect the true VDD_PRI supply voltage used.

Table 24. Register 5

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15

RESERVED

This bit must be set to 0

14

RESERVED

This bit must be set to 0

13

RESERVED

This bit must be set to 0

12

RESERVED

This bit must be set to 0

11

RESERVED

This bit must be set to 0

10

RESERVED

This bit must be set to 0

9

RESERVED

This bit must be set to 0

Output Channel 1 Type Selection:

00, 01

→ LVDS

8:7

SEL_DRVR_CH1[1:0]

10

→ CML

11

→ PECL

Output Channel 1

Output channel 1 enable:

00

→ Disable

6:5

EN _CH1[1:0]

01

→ Enable

10

→ Drive static 0

11

→ Drive static 1

Output Channel 0 Type Selection:

00, 01

→ LVDS

4:3

SEL_DRVR_CH0[1:0]

10

→ CML

11

→ PECL

Output Channel 0

Output channel 0 enable:

00

→ Disable

2:1

EN_CH0[1:0]

01

→ Enable

10

→ Drive static 0

11

→ Drive static 1

Output Channels 0 and 1 Supply Voltage Selection:

Output Channels 0

0

SUPPLY_CH0_1 (1)

0

→ 1.8 V

and 1

1

→ 2.5/3.3 V

(1)

It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 25. Register 6

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15

RESERVED

This bit must be set to 0

14

RESERVED

This bit must be set to 0

13

RESERVED

This bit must be set to 0

12

RESERVED

This bit must be set to 0

11

RESERVED

This bit must be set to 0

10

RESERVED

This bit must be set to 0

9

RESERVED

This bit must be set to 0

8

RESERVED

This bit must be set to 0

Output Channels 0

Output channels 0 and 1 8-b output integer divider setting

7:0

OUTDIV0_1[7:0]

and 1

(Divider value is register value +1)

60

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