CDCM6208V1RGZT datasheet(59/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

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SCAS931A – MAY 2012 – REVISED JUNE 2012

Table 22. Register 3 (continued)

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

Output Channel Dividers Synchronization Enable:

5

SYNCN

Output Divider

0

→ Forces synchronization

1

→ Exits synchronization

PLL/VCO Calibration Enable:

4

ENCAL

PLL/VCO

0

→ Disable

1

→ Enable

PLL Prescaler 1 Integer Divider Selection:

00

→ Divide-by-4

01

→ Divide-by-5

3:2

PS_B[1:0]

PLL Prescaler Divider B

10

→ Divide-by-6

11

→ RESERVED

used for Y2, Y3, Y6, and Y7

PLL Prescaler 0 Integer Divider Selection:

00

→ Divide-by-4

01

→ Divide-by-5

1:0

PS_A[1:0]

PLL Prescaler Divider A

10

→ Divide-by-6

11

→ RESERVED

used in PLL feedback, Y0, Y1, Y4, and Y5

Table 23. Register 4

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

Smart MUX Pulse Width Selection. This bit controls the Smart MUX

delay and waveform reshaping.

00

→ PLL Smart MUX Clock Delay and Reshape Disabled (default

15:14

SMUX_PW[1:0]

in all pin modes)

01

→ PLL Smart MUX Clock Delay Enable

10

→ PLL Smart MUX Clock Reshape Enable

11

→ PLL Smart MUX Clock Delay and Reshape Enable

Smart MUX Mode Selection:

Reference Input Smart

0

→ Auto select

MUX

13

SMUX_MODE_SEL

1

→ Manual select

Note: in Auto select mode, both input buffers must be enabled. Set

R4.5 = 1 and R4.2 = 1

Smart MUX Selection for PLL Reference:

0

→ Primary

12

SMUX_REF_SEL

1

→ Secondary (only if REF_SEL pin is high)

This bit is ignored when smartmux is set to auto select (e.g. R4.13 =

0). See Table 13 for details.

Primary Input (R) Divider Selection"

11:8

CLK_PRI_DIV[3:0]

Primary Input Divider

0000

→ Divide by 1

1111

→ Divide by 16

Secondary Input Buffer Type Selection:

00

→ CML

7:6

SEC_SELBUF[1:0]

01

→ LVDS

10

→ LVCMOS

Secondary Input

11

→ Crystal

Secondary input enable:

5

EN_SEC_CLK

0

→ Disable

1

→ Enable

Primary Input Buffer Type Selection:

00

→ CML

4:3

PRI_SELBUF[1:0]

01

→ LVDS

10

→ LVCMOS

Primary Input

11

→ LVCMOS

Primary input enable:

2

EN_PRI_CLK

0

→ Disable

1

→ Enable

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