CDCM6208V1RGZT datasheet(6/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

Table 4. CDCM6208 Pin Assignments

I/O

TYPE

DESCRIPTION

NAME

Number

PRI_REFP

8

Input

Universal

Primary Reference Input +

PRI_REFN

9

Input

Universal

Primary Reference Input -

Supply pin for reference inputs to set between 1.8, 2.5 or 3.3 V. If the

VDD_PRI_REF

7

PWR

Analog

primary input is unused (e.g. XTAL mode only), this supply can be set to

0 V to minimize device power consumption.

SEC_REFP

11

Input

Universal

Secondary Reference Input +

SEC_REFN

12

Input

Universal

Secondary Reference Input -

Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V. If

VDD_SEC_REF 10

PWR

Analog

the secondary input is unused, this supply can be set to 0 V to minimize

device power consumption.

Manual Reference Selection MUX for PLL. In SPI or I2C mode the

LVCMOS

reference selection is also controlled through Register 4 bit 12.REF_SEL

REF_SEL

6

Input

w/ 50k

Ω pull-up

= 0 (

≤ VIL): selects PRI_REFREF_SEL = 1 (≥ VIH): selects SEC_REF

(when Reg 4.12 = 1). See Table 7 for detail.

ELF

41

Output

Analog

External loop filter pin for PLL

Y0_P

14

Output

Universal

Output 0 Positive Terminal

Y0_N

15

Output

Universal

Output 0 Negative Terminal

Y1_P

17

Output

Universal

Output 1 Positive Terminal

Y1_N

16

Output

Universal

Output 1 Negative Terminal

VDD_Y0_Y1 (2

13, 18

PWR

Analog

Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V or 3.3 V

pins)

Y2_P

20

Output

Universal

Output 2 Positive Terminal

Y2_N

21

Output

Universal

Output 2 Negative Terminal

Y3_P

23

Output

Universal

Output 3 Positive Terminal

Y3_N

22

Output

Universal

Output 3 Negative Terminal

VDD_Y2_Y3 (2

19, 24

PWR

Analog

Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V or 3.3 V

pins)

Y4_P

26

Output

Universal

Output 4 Positive Terminal

Y4_N

25

Output

Universal

Output 4 Negative Terminal

VDD_Y4

27

PWR

Analog

Supply pin for output 4 to set between 1.8 V, 2.5 V or 3.3 V

Y5_P

29

Output

Universal

Output 5 Positive Terminal

Y5_N

28

Output

Universal

Output 5 Negative Terminal

VDD_Y5

30

PWR

Analog

Supply pin for output 5 to set between 1.8 V, 2.5 V or 3.3 V

Y6_P

32

Output

Universal

Output 6 Positive Terminal

Y6_N

33

Output

Universal

Output 6 Negative Terminal

VDD_Y6

31

PWR

Analog

Supply pin for output 6 to set between 1.8 V, 2.5 V or 3.3 V

Y7_P

35

Output

Universal

Output 7 Positive Terminal

Y7_N

36

Output

Universal

Output 7 Negative Terminal

VDD_Y7

34

PWR

Analog

Supply pin for output 7 to set between 1.8 V, 2.5 V or 3.3 V

Analog power supply for PLL/VCO; This pin is sensitive to power supply

VDD_VCO

39

PWR

Analog

noise; The supply of this pin and the VDD_PLL2 supply pin can be

combined as they are both analog and sensitive supplies;

VDD_PLL1

37

PWR

Analog

Analog Power Supply Connections

Analog Power Supply Connections; This pin is sensitive to power supply

VDD_PLL2

38

PWR

Analog

noise; The supply of VDD_PLL2 and VDD_VCO can be combined as

these pins are both power-sensitive, analog supply pins

Digital Power Supply Connections; This is also the reference supply

DVDD

48

PWR

Analog

voltage for all control inputs and must match the expected input signal

swing of control inputs.

GND

PAD

PWR

Analog

Power Supply Ground and Thermal Pad

STATUS0

46

Output

LVCMOS

Status pin 0 (see Table 28 for details)

6

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