CDCM6208V1RGZT datasheet(58/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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58 / 78 page

CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

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Table 19. Register 0 (continued)

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

PLL Internal Loop Filter Resistor (R3) Selection

000

→ 10 Ω

001

→ 30 Ω

010

→ 60 Ω

PLL Internal Loop Filter

6:4

LF_R3[2:0]

011

→ 100 Ω

(R3)

100

→ 530 Ω

101

→ 1050 Ω

110

→ 2080 Ω

111

→ 4010 Ω

PLL Charge Pump Current Setting

000

→ 500 µA

001

→ 1.0 mA

010

→ 1.5 mA

3:1

PLL_ICP[2:0]

PLL Charge Pump

011

→ 2.0 mA

100

→ 2.5 mA

101

→ 3.0 mA

110

→ 3.5 mA

111

→ 4.0 mA

This bit is tied to zero statically, and it is recommended to set to 0

0

RESERVED

when writing to register.

Table 20. Register 1

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

PLL Reference 14-b Divider Selection

15:2

PLL_REFDIV[13:0]

PLL Reference Divider

(Divider value is register value +1)

1:0

PLL_FBDIV1[9:8]

PLL Feedback Divider 1

PLL Feedback 10-b Divider Selection, Bits 9:8

Table 21. Register 2

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

PLL Feedback 10-b Divider Selection, Bits 7:0

15:8

PLL_FBDIV1[7:0]

PLL Feedback Divider 1

(Divider value is register value +1)

PLL Feedback 8-b Divider Selection

7:0

PLL_FBDIV0[7:0]

PLL Feedback Divider 0

(Divider value is register value +1)

Table 22. Register 3

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15:13

RESERVED

These bits must be set to 0

Reference clock status enable on Status 1 pin:

12

ST1_SEL_REFCLK

0

→ Disable

1

→ Enable (See Table 13 for full description)

Loss-of-reference Enable on Status 1 pin:

11

ST1_LOR_EN

0

→ Disable"

1

→ Enable (See Table 13 for full description)

PLL Lock Indication Enable on Status 1 pin:

10

ST1_PLLLOCK_EN

0

→ Disable

1

→ Enable (See Table 13 for full description)

Device Status

Reference clock status enable on Status 0 pin:

9

ST0_SEL_REFCLK

0

→ Disable

1

→ Enable (See Table 13 for full description)

Loss-of-reference Enable on Status 0 pin:

8

ST0_LOR_EN

0

→ Disable

1

→ Enable (See Table 13 for full description)

PLL Lock Indication Enable on Status 0 pin:"

7

ST0_PLLLOCK_EN

0

→ Disable

1

→ Enable (See Table 13 for full description)

Device Reset Selection:

6

RSTN

Device Reset

0

→ Device In Reset (retains register values)

1

→ Normal Operation

58

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