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CDCM6208V1RGZT Datasheet(PDF) 55 Page - Texas Instruments |
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CDCM6208V1RGZT Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 78 page  OSC = OUT (O × PS_A) f f SEC_REF VCO = M (N × PS_A) f f PRI_REF VCO = (M × R) (N × PS_A) f f CDCM6208 www.ti.com SCAS931A – MAY 2012 – REVISED JUNE 2012 Table 18. I2C TIMING SYMBOL PARAMETER STANDARD MODE FAST MODE UNITS MIN MAX MIN MAX fSCL SCL Clock Frequency 0 100 0 400 kHz tsu(START) START Setup Time (SCL high before SDA 4.7 0.6 μs low) th(START) START Hold Time (SCL low after SDA low) 4.0 0.6 μs tw(SCLL) SCL Low-pulse duration 4.7 1.3 μs tw(SCLH) SCL High-pulse duration 4.0 0.6 μs th(SDA) SDA Hold Time (SDA valid after SCL low) 0 (1) 3.45 0 0.9 μs tsu(SDA) SDA Setup Time 250 100 ns tr-in SCL / SDA input rise time 1000 300 ns tf-in SCL / SDA input fall time 300 300 ns tf-out SDA Output fall time from VIH min to VIL max 250 250 ns with a bus capacitance from 10 pF to 400 pF tsu(STOP) STOP Setup Time 4.0 0.6 μs tBUS Bus free time between a STOP and START 4.7 1.3 μs condition tglitch_filter Pulse width of spikes suppressed by the 75 300 75 300 ns input glitch filter (1) The I2C master must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. For additional information refer to the I2C-Bus specification, Version 2.1 (January 2000); the CDCM6208 meets the switching characteristics for standard mode and fast mode transfer. CONFIGURING THE PLL The CDCM6208 allows configuring the PLL to accommodate various input and output frequencies either through an I2C or SPI programming interface or in the absence of programming, the PLL can be configured through control pins. The PLL can be configured by setting the Smart Input MUX, Reference Divider, PLL Loop Filter, Feedback Divider, Prescaler Divider and Output Dividers. For the PLL to operate in closed loop mode, the following condition in Equation 2 has to be met when using primary input for the reference clock and the condition in Equation 3 has to be met when using secondary input for the reference clock. (2) (3) In Equation 2 and Equation 3, ƒPRI_REF is the reference input frequency on the primary input and ƒSEC_REF is the reference input frequency on the secondary input, R is the reference divider, M is the input divider, N is the feedback divider, and PS_A the prescaler divider A. The output frequency, ƒOUT, is a function of ƒVCO, the prescaler A, and the output divider (O), and is given by Equation 4. (Use PS_B in for outputs 2, 3, 6, and 7). (4) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 55 Product Folder Link(s): CDCM6208 |
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