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CDCM6208V1RGZT Datasheet(PDF) 54 Page - Texas Instruments |
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CDCM6208V1RGZT Datasheet(HTML) 54 Page - Texas Instruments |
54 / 78 page STOP START STOP tBUS tSU(START) SDA SCL th(START) tr(SM) tSU(SDATA) tW(SCLL) tW(SCLH) th(SDATA) tr(SM) tf(SM) tf(SM) tSU(STOP) VIH(SM) VIL(SM) VIH(SM) VIL(SM) ACK CDCM6208 SCAS931A – MAY 2012 – REVISED JUNE 2012 www.ti.com For "Register Write/Read" operations, the I2C master can individually access addressed registers, that are made of two 8-bit data bytes. Table 16. I2C SLAVE ADDRESS BYTE A6 A5 A4 A3 A2 AD1 AD0 R/W 1 0 1 0 1 0 0 1/0 1 0 1 0 1 0 1 1/0 1 0 1 0 1 1 0 1/0 1 0 1 0 1 1 1 1/0 Table 17. Generic Programming Sequence S Start Condition Sr Repeated Condition R/W 1 = Read (Rd) from slave; 0 = Write (Wr) to slave A Acknowledge (ACK = 0 and NACK = 1) P Stop Condition Master to Slave Transmission Slave to Master Transmission Figure 49. Register Write Programming Sequence 1 7 1 1 8 1 8 1 8 1 8 1 1 SLAVE Register Register Data Data S Wr A A A A A P Address Address Address Byte Byte Figure 50. Register Read Programming Sequence 1 7 1 1 8 1 8 1 1 1 1 1 8 1 8 1 1 SLAVE Register Register Slave Data Data S Wr A A A S Rd A A A P Address Address Address Address Byte Byte Figure 51. I2C Timing Diagram 54 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCM6208 |
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