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CDCM6208V1RGZT Datasheet(PDF) 52 Page - Texas Instruments |
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CDCM6208V1RGZT Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 78 page  SCL SCS SDO t4 t 5 t2 t3 t 7 t 6 t1 SDI t8 A31 D0 D1 D15 D1 D0 A30 '21¶7 &$5( '21¶7 &$5( tri-state SCS SCL SCI WRITE READ SCI SCO HI-Z 16-BIT COMMAND 16-BIT DATA '21¶7 &$5( A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 CDCM6208 SCAS931A – MAY 2012 – REVISED JUNE 2012 www.ti.com Figure 46. CDCM6208 SPI Port Message Sequencing Figure 47. CDCM6208 SPI Port Timing Table 15. SPI TIMING PARAMETER MIN TYP MAX UNITS fClock Clock Frequency for the SCL 20 MHz t1 SPI_LE to SCL setup time 10 ns t2 SDI to SCL setup time 10 ns t3 SDO to SCL hold time 10 ns t4 SCL high duration 25 ns t5 SCL low duration 25 ns t6 SCL to SCS Setup time 10 ns t7 SCS Pulse Width 20 ns t8 SDI to SCL Data Valid (First Valid Bit after SCS) 10 ns I2C SERIAL INTERFACE With SI_MODE1=0 and SI_MODE0=1 the CDCM6208 enters I 2C mode. The I2C port on the CDCM6208 works as a slave device and supports both the 100 kHz standard mode and 400 kHz fast mode operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses of less than 50 ns duration. The inputs of the device also incorporates a Schmitt trigger at the SDA and SCL inputs to provide receiver input hysteresis for increased noise robustness. 52 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCM6208 |
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