CDCM6208V1RGZT datasheet(51/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

SDO

(#34)

Data out

SCS (#37)

LVCMOS

&

0

SDO internal

enable signal

D

15

D

14

D

13

D

12

D

11

D

10

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Fixed (4 bits)

Register Address (11 bits)

Data Payload (16 bits)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Message Field Definition

Bit Definition

Order of Transmission

First Out

Examples:

Read Register 4:

1|000 0|000 0000 0100| xxxx xxxx xxxx xxxx

Write 0xF0F1 to Register 5:

0|000 0|000 0000 0101| 1111 0000 1111 0001

MSB

LSB

CDCM6208

www.ti.com

SCAS931A – MAY 2012 – REVISED JUNE 2012

The host must present data to the device MSB first. A message includes a transfer direction bit, an address field,

and a data field as depicted in Figure 44

Figure 44. CDCM6208 SPI Message Format

Writing to the CDCM6208

To initiate a SPI data transfer, the host asserts the SCS (serial chip select) pin low. The first rising edge of the

clock signal (SCL) transfers the bit presented on the SDI pin of the CDCM6208. This bit signals if a read (first bit

high) or a write (first bit low) will transpire. The SPI port shifts data to the CDCM6208 with each rising edge of

SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the target register in

the register file. The 16 bits that follow are the data payload. If the host sends an incomplete message, (i.e. the

host de-asserts the SCS pin high prior to a complete message transmission), then the CDCM6208 aborts the

transfer, and device makes no changes to the register file or the hardware. Figure 46 shows the format of a write

transaction on the CDCM6208 SPI port. The host signals the CDCM6208 of the completed transfer and disables

the SPI port by de-asserting the SCS pin high.

Reading from the CDCM6208

As with the write operation, the host first initiates a SPI transfer by asserting the SCS pin low. The host signals a

read operation by shifting a logical high in the first bit position, signaling the CDCM6208 that the host is imitating

a read data transfer from the device. During the portion of the message in which the host specifies the

CDCM6208 register address, the host presents this information on the SDI pin of the device (for the first 15 clock

cycles after the W/R bit). During the 16 clock cycles that follow, the CDCM6208 presents the data from the

register specified in the first half of the message on the SDO pin. The SDO output is 3-stated anytime SCS is

high, so that multiple SPI slave devices can be connected to the same serial bus. The host signals the

CDCM6208 that the transfer is complete by de-asserting the SCS pin high.

Figure 45.

Block Write/Read Operation

The device supports a block write and block read operation. The host need only specify the lowest address of the

sequence of addresses that the host needs to access. The CDCM6208 will automatically increment the internal

register address pointer if the SCS pin remains low after the SPI port finishes the initial 32-bit transmission

sequence. Each transmission of 16 bits (a data payload width) results in the device automatically incrementing

the address pointer (provided the SCS pin remains active low for all sequences).

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