CDCM6208V1RGZT datasheet(49/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

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SCAS931A – MAY 2012 – REVISED JUNE 2012

Table 13. CDCM6208 Status Pin Definition List (continued)

STATUS

SIGNAL Type

SIGNAL NAME

REGISTER BIT Description

SIGNAL Name

NO.

PLL_UNLOCK

LVCMOS

STATUS0/1

Reg 3.10

Indicates unlock status for PLL (digital):

Reg 3.7

PLL locked

→ Q21.02 = 0 and VSTATUS0/1= VIH

PLL unlocked

→ Q21.2 = 1 and VSTATUS0/1= VILSee note

(1)

Note 2: I f the smartmux is enabled and both reference clocks stall,

the STATUSx output signal will 98% of the time indicate the LOS

condition with a static high signal. However, in 2% of the cases, the

LOS detection engine erroneously stalls at a state where the

STATUSx output PLL lock indicator will signalize high for 511 out of

every 512 PFD clock cycles.

(1)

The reverse logic between the register Q21.2 and the external output signal on STATUS0 or STATUS1.

NOTE

It is recommended to assert only one out of the three register bits for each of the status

pins. For example, to monitor the PLL lock status on STATUS0 and the selected reference

clock sources on STATUS1 output, the device register settings would be Q3.11 = Q3.9 =

1 and Q3.12 = Q3.10 = Q3.8 = Q3.7 = 0. If a status pin is unused, it is recommended to

set the according 3 register bits to zero (e.g. Q3[12:9] = 0 ofr STATUS0 = 0). If more than

one bit is enabled for each STATUS signal, the function becomes OR'ed. For example, if

Q3.11 = Q3.10 = 1 and Q3.12 = 0, the STATUS0 output would be high either if the device

goes out of lock or the selected reference clock signal is lost.

PLL lock detect

The PLL lock detection circuit is a digital detection circuit and detects any frequency error, even a single cycle

slip. The PLL unlock is signalized when a certain number of cycle slips have been exceeded, at which point the

counter is reset. A frequency error of 2% will cause PLL unlock to stay low. A 0.5% frequency error shows up as

toggling the PLL lock output with roughly 50% duty cycle at roughly 1/1000 th of the input reference frequency to

the device. A frequency error of 1ppm would show up as rare toggling low for a duration of approximately 1000

input clock cycles. If the customer system plans using PLL lock to toggle a system reset, then consider adding an

RC filter on the PLL LOCK output (Status 1 or Status 0) to avoid rare cycle slips from triggering an entire system

reset.

Interface and control

The host (DSP, Microcontroller, FPGA, etc) configures and monitors the CDCM6208 via the SPI or I2C port. The

host reads and writes to a collection of control/status bits called the register file. Typically, a hardware block is

controlled and monitored via a specific grouping of bits located within the register file. The host controls and

monitors certain device-wide critical parameters directly via control/status pins. In the absence of a host, the

CDCM6208 can be configured to operate in pin mode where the control pins [PIN0-PIN4] can be set

appropriately to generate the necessary clock outputs out of the device.

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