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CDCM6208V1RGZT Datasheet(PDF) 40 Page - Texas Instruments |
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CDCM6208V1RGZT Datasheet(HTML) 40 Page - Texas Instruments |
40 / 78 page De-Serializer Serializer TX REF CLOCK TX PLL serial data with embedded clock CDR RX REF CLOCK fhigh=BWTX PLL RX PLL flow=BWRX PLL fhigh flow HTransfer(f) = HTXPLL * ( 1 - HRXPLL) flow=1.875MHz for 10GbE fhigh=20MHz for 10GbE CDCM6208 SCAS931A – MAY 2012 – REVISED JUNE 2012 www.ti.com Figure 38. Serial Link Jitter Budget Explanation Jitter Considerations in ADC and DAC Systems A/D converter and D/A converter are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular frequency band and also have maximum spur level requirements to achieve maximum noise floor sensitivity. The following test results were achieved connecting the CDCM6208 to ADC and DACs: 40 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCM6208 |
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