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CDCM6208V1RGZT Datasheet(PDF) 39 Page - Texas Instruments

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Part # CDCM6208V1RGZT
Description  2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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CDCM6208V1RGZT Datasheet(HTML) 39 Page - Texas Instruments

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Y2
PWR ramp VDD_Y2_Y3
Y0
CDCM6208
www.ti.com
SCAS931A – MAY 2012 – REVISED JUNE 2012
Figure 37. Sequencing the Output Turn-on Through Sequencing the Output Supplies. Output Y2 Powers
Up While Output Y0 is Already Running.
Jitter Considerations in Serdes Systems
The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using
Serializer and De-serializer implementation (e.g. 10 GigEthernet). To fully estimate the clock jitter impact on the
link budget requires to understand the transmit PLL bandwidth and the receiver CDR bandwidth. As can be seen
in Figure 38, the bandwidth of TX and RX is the frequency range in which clock jitter adds without any
attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate clock
jitter with a 20 dB/dec or even steeper roll-off.
Copyright © 2012, Texas Instruments Incorporated
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