CDCM6208V1RGZT datasheet(37/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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CDCM6208

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SCAS931A – MAY 2012 – REVISED JUNE 2012

The fractional output divider requires an input frequency from 400 MHz to 800 MHz, and outputs any frequency

equal or less than 400 MHz (the minimum fractional output divider setting is 2). The fractional divider block has a

first stage integer pre-divide followed by a fractional sigma-delta output divider block that is deep enough such as

to generate any output frequency in the range of 0.78 MHz to 400 MHz from any input frequency in the range of

400 MHz to 800 MHz with a worst case frequency accuracy of no more than ±1ppm. The fractional values

available are all possible 20-b representation of fractions within the following range:

•

1.0

≤ ƒracDIV ≤ 1.9375

•

2.0

≤ ƒracDIV ≤ 3.875

•

4.0

≤ ƒracDIV ≤ 5.875

•

x.0

≤ ƒracDIV ≤ (x + 1) + 0.875 with x being all even numbers from x = 2, 4, 6, 8, 10, ...., 254

•

254.0

≤ ƒracDIV ≤ 255.875

•

256.0

≤ ƒracDIV ≤ 256.99999

The CDCM6208 user GUI comprehends the fractional divider limitations best and it is therefore recommended to

use the user GUI to comprehend frequency planning.

The fractional divider output jitter is a function of fractional divider input frequency and furthermore depends on

which bits are exercised within the fractional divider. Exercising only MSB or LSB bits provides better jitter than

exercising bits near the center of the fractional divider. Jitter data are provided in this document, and vary from

50 ps-pp to 200 ps-pp, when the device is operated as a frequency synthesizer with high PLL bandwidths

(approximately 100 kHz to 400 kHz). When the device is operated as a jitter cleaner with low PLL bandwidths (<

1 kHz), its additive total jitter increases by as much as 30 ps-pp. The fractional divider can be used in integer

mode. However, if only an integer divide ratio is needed, it is important to disable the corresponding fractional

divider enable bit, which engages the higher performing integer divider.

OUTPUT SYNCHRONIZATION

Both types of output dividers can be synchronized using the SYNCN signal. For the CDCM6208, this signal

comes from the SYNCN pin or the soft SYNCN register bit R3.5. The most common way to execute the output

synchronization is to toggle the SYNCN pin. When SYNC is asserted (V SYNCN ≤ VIL), all outputs are disabled

(high-impedance) and the output dividers are reset. When SYNC is de-asserted (V SYNCN ≥ VIH), the device first

internally latch the signal, then retimes the signal with the pre-scaler, and finally turns all outputs simultaneously

on. The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the SYNC pin

assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles. For one

particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle.

The SYNC feature is particularly helpful in systems with multiple CDCM6208. If SYNC is released simultaneously

for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices configured to

identical pre-scaler settings. For devices with varying pre-scaler settings, the total part-to-part skew uncertainty

due to sync remains ±2 clock cycles.

Outputs Y0, Y1, Y4, and Y5 are aligned with the PS_A output while outputs Y2, Y3, Y6, and Y7 are aligned with

the PS_B output). All outputs Y[7:0] turn on simultaneously, if PS_B and PS_A are set to identical divide values

(PS_A=PS_B).

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