CDCM6208V1RGZT datasheet(36/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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÷ 1, 2 or 3

Pre-Scaler

output clock

398-800MHz

Limit: 200-400MHz

÷ 4, 5 or 6

VCO

2.39-2.55GHz

2.94-3.13GHz

Pre-Scaler PS_A or PS_B

FracDiv Pre Divider

Reg 9.12:10

Reg 12.12:10

Reg 15.12:10

Reg 18.12:10

÷ 1 to 256

Reg 10.11:4

Reg 13.11:4

Reg 16.11:4

Reg 19.11:4

Integer Divider

Reg 3.4:0

.xxx

Reg 10.3:0 + Reg 11

Reg 13.3:0 + Reg 14

Reg 16.3:0 + Reg 17

Reg 19.3:0 + Reg 20

Fractional Divider (simplified)

Fractional division

CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

LVPECL-like: Outputs Y[3:0] support LVPECL-like signaling. The actual output stage uses a CML structure but

drives the same signal amplitude and rise time as true emitter coupled logic output stages. The LVPECL-like

outputs should be AC-coupled, and contrary to standard PECL designs, no external termination resistor to VCC-

2V is used (fewer components for lowest BOM cost). See reference schematic Figure 56 for an example. The

supply voltage for outputs configured LVPECL-like is recommended to be 3.3 V, though even 1.8 V provides

nearly the same output swing and performance at much lower power consumption.

CML: Outputs Y[3:0] support standard CML signaling. The supply voltage for outputs configured CML can be

selected freely between 1.8 V and 3.3 V. A true CML receiver can be driven DC coupled. All other differential

receiver should connected using AC coupling. See reference schematic Figure 56 for a circuit example.

HCSL: Outputs Y[7:4] support HCSL signaling. The supply voltage for outputs configured HCSL can be selected

freely between 1.8 V and 3.3 V. HCSL is referenced to GND, and requires external 50

Ω termination to GND.

See reference schematic for an example.

CMOS: Outputs Y[7:4] support 1.8 V, 2.5 V, and 3.3 V CMOS signaling. A fast or reduced slew rate can be

selected through register programming. Each differential output port can drive one or two CMOS output signals.

Both signals are “in-phase”, meaning their phase offset is zero degree, and not 180

˚. The output swing is set by

providing the according supply voltage (e.g. if VDD_Y4=2.5 V, the output swing on Y4 will be 2.5 V CMOS).

Outputs configured for CMOS should only be terminated with a series-resistor near the device output to preserve

the full signal swing. Terminating CMOS signals with a 50

Ω resistor to GND would reduce the output signal

swing significantly.

Integer Output Divider (IO)

Each integer output divider is made up of a continuous 10-b counter. The output buffer itself contributes only little

to the total device output jitter due to a low output buffer phase noise floor. The typical output phase noise floor

at an output frequency of 122.88 MHz at 20 MHz offset from the carrier measures: LVCMOS: -157.8 dBc/Hz,

LVDS: -158 dBc/Hz, LVPECL: -158.25 dBc/Hz, HCSL: -160 dBc/Hz. Therefore, the overall contribution of the

output buffer to the total jitter is approximately 50 fs-rms (12 k - 20 MHz). An actual measurement of phase noise

floor with different output frequencies for one nominal until yielded the following:

Table 8.

fOUT

LVDS (Y0)

PECL (Y0)

CML (Y0)

HCSL (Y4)

CMOS 3p3V (Y7)

737.28 MHz

-154.0 dBc/Hz

-154.8 dBc/Hz

-154.4 dBc/Hz

-153.1 dBc/Hz

-150.9 dBc/Hz

368.64 MHz

-157.0 dBc/Hz

-155.8 dBc/Hz

-156.4 dBc/Hz

-153.9 dBc/Hz

-153.1 dBc/Hz

184.32 MHz

-157.3 dBc/Hz

-158.6 dBc/Hz

158.1 dBc/Hz

-154.7 dBc/Hz

-156.2 dBc/Hz

92.16 MHz

-161.2 dBc/Hz

-161.6 dBc/Hz

-161.4 dBc/Hz

-155.2 dBc/Hz

-159.4 dBc/Hz

46.08 MHz

-162.2 dBc/Hz

-165.0 dBc/Hz

-163.0 dBc/Hz

-154.0 dBc/Hz

-162.8 dBc/Hz

FRACTIONAL Output Divider (FOD)

The CDCM6208 incorporates a fractional output divider on Y[7:4], allowing these outputs to run at non-integer

output divide ratios of the PLL frequencies. This feature is useful when systems require different, unrelated

frequencies. The fractional output divider architecture is shown in Figure 35.

Figure 35. Fractional Output Divider Principle Architecture (Simplified Graphic, not Showing Output

Divider Bypass Options)

36

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